AMD Answer 75745
The GEM controller can erroneously trigger an
amba_error interrupt event via bit 6 of the
ISR register (also reflected in bit 4 of the
Tx_Status register) when a large send offload (LSO) is included in the
hardware configuration (via the
IP_Config6[pbuf_lso] configuration option) and LSO functionality is
enabled in the buffer descriptors.
Other than reporting this error incorrectly, there is no observed functional issue and the LSO feature can continue to be relied upon. This is classified as a minor hardware issue because the falsely reported event can easily be masked and ignored.
This is a third-party errata; this issue will not be fixed.