The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 2/05/2024 Version 1.5 | |
| Devices, In RP Mode, ME/BME Bit Does Not Gate Requests, CPM5 CML HA WR_BUFFER RAM Is 96 Deep Instead Of 128, GTM TX CDM ESD Tolerance Is Lower Than The Production Target | Added XCVM2302, XCVM2502, and XCVM2902 devices and associated issues. |
| Primary Boot Is Not Supported With eMMC Devices That Require CMD6 Busy Time Greater Than 1 ms | Added PMC primary boot eMMC issue. |
| 6/7/2023 Version 1.4 | |
| Devices | Added XQVM1502 device. |
| 1/26/2023 Version 1.3 | |
| Devices | Added XQVM1402 and XCVM1502 devices. |
| Errata Summary | Updated Table 1. |
| Readback Capture Is Not Supported | Removed issue: Not a deviation from the production specification. |
| Control IMUX Registers Are Not Supported | Removed issue: Not a deviation from the production specification. |
| In RC Mode With SMMU Enabled, CCI Transaction Ordering Is Not Followed Between Different Shareability Domain Memories That Have Same AXI ID | New errata issue. |
| 11/09/2022 Version 1.2 | |
| Devices | Added XQVM1802, XCVM1402, and XCVM1302 devices. |
| IPOR Issued After An SRST Causes A Boot Failure | New errata issue. |
| 11/12/2021 Version 1.1 | |
| HDIO/MIO: When An Output Is Powered At 3.3V Or 2.5V, A Race Condition Can Exist Between Data And Tristate | New errata issue. |
| 4/14/2021 Version 1.0 | |
| Initial release. | N/A |