This section describes the hardware configurations supported by lwIP. The key components of the hardware system include:
- Processor: MicroBlaze, Cortex-A9, Cortex-A53, or Cortex-R5 processor. The Cortex-A9 processor applies to Zynq systems. The Cortex-A53 and Cortex-R5 processors apply to Zynq UltraScale+ MPSoC systems. The Cortex-A72 and Cortex-R5F processors apply to Versal adaptive SoC systems.
- MAC: LwIP supports axi_ethernetlite, axi_ethernet, and Gigabit Ethernet controller and MAC (GigE) cores.
- Timer: To maintain TCP timers, lwIP use raw API based applications. It requires periodic calling of certain functions by the application. An application achieve this by registering an interrupt handler with a timer. To maintain TCP timers, lwIP raw API based applications require that certain functions are called at periodic intervals by the application. An application can do this by registering an interrupt handler with a timer.
- DMA: For axi_ethernet based systems, the axi_ethernet cores can be configured with a soft DMA engine (AXI DMA and MCDMA) or a FIFO interface. There is a built-in DMA for GigE-based Zynq, Zynq UltraScale+ MPSoC, and Versal adaptive SoC systems which does not require extra configuration. Same applies to axi_ethernetlite based systems, which have their built-in buffer management provisions.
The following figure shows a sample system architecture with a Zynq Ultrascale+ MPSoC device utilizing the axi_ethernet core with DMA.
Figure 1. AXI Ethernet subsystem with DMA on Zynq Ultrascale+ MPSoC
