The PC-CFR core processes control and data through industry-standard AXI4 interfaces that allow immediate logic-free connection to other AMD IP components and to any general environment. The control interface is AXI4-Lite compliant and the data interface is AXI4-Stream compliant. The control interface provides access to a set of configuration registers and a pulse coefficient RAM and the data interface is used for streaming data in/out of the core. The data flow is unidirectional with no rate or bit-width change. A typical CFR application consists of multiple iterations and multiple antennas that can be configured through the Vivado Integrated Design Environment (IDE). The core is configured for a particular application through the control interface. In particular, the contents of the pulse coefficient RAM are related to the spectrum of the signal being transmitted.
The PC-CFR LogiCORE IP Product Guide (PG097) documents how to produce these coefficients, and specific details are provided for the WCDMA, CDMA2000, WiMAX, TD-SCDMA, GSM, LTE, and 5G-NR air interfaces. Mixed-mode signal operation is also supported. Pulse coefficients can be pre-configured at generation time through a .coe file or configured in operation through the control interface. There is also provision for a shadow bank of coefficients to be loaded and then activated with a select signal, to cater to applications where fast dynamic switching is required. Functions that can be run with MATLAB® are supplied for simulation and design of the cancellation pulse.
The core can be configured for clock-to-sample ratios of 1, 2, 3, and 4 and for algorithmic complexity, allowing FPGA resources to be minimized for a given application. The algorithmic complexity is the number of hardware resources available to cancel the signal peaks. These are called cancellation pulse generators (CPGs).