The XDMA/QDMA Simulation IP core is a SystemC-based abstract simulation model for XDMA/QDMA and enables the emulation of Xilinx® Runtime (XRT) to device communication. With this IP a Xilinx Runtime host application (through OpenCL™ APIs) can communicate with kernels, memories, and streaming resources, but the communication is at the transaction level and does not model PCIe® -level communication as in actual hardware.
Being a System- based model, the memory mapped AXI4 and AXI4-Stream interfaces on this IP are SystemC xTLM sockets (an extension of SystemC TLM 2.0 sockets). The Vivado® IP integrator can handle the xTLM sockets and can connect it to other models which are based on SystemC or it can also connect to RTL IPs. This IP is intended to be used only in IP integrator and to enable hardware emulation support for the Vitis™ unified software platform. It is not intended, nor tested, for other use cases.