IP Facts - 2.0 English

400G IEEE 802.3bs Reed-Solomon Forward Error Correction (PB065)

Document ID
Release Date
2.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Versal™ , UltraScale™ , UltraScale+™ 2
Supported User Interfaces AXI4-Stream
Resources Performance and Resource Utilization web page
Provided with Core
Design Files Encrypted RTL
Example Design N/A
Test Bench Not Provided
Constraints File Xilinx Constraints File
Simulation Model Encrypted Verilog
Supported S/W Driver N/A
Tested Design Flows 3
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado® Design Suite
Release Notes and Known Issues Master Answer Record: 73658
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. -1 speed grades are not supported for these devices.
  3. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.