|
Core Specifics |
| Supported Device Family |
Virtex UltraScale and Virtex UltraScale+
|
| Supported User Interfaces |
N/A |
| Provided with Core
|
| Design Files |
Register Transfer Level (RTL) |
| Example Design |
Provided with Core |
| Test Bench |
Not Provided |
| Constraints File |
Provided with Core |
| Simulation Model |
Provided with Example Design |
| Supported S/W Driver |
N/A |
| Tested Design Flows
1
|
| Design Entry |
Vivado® Design Suite
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: N/A. Documented in this user
guide. |
|
Xilinx
Support web page
|
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
|