Features - 1.2 English

• AXI4-Stream/AXI4 protocol support per lane
• Up to 52-bit sideband signal per lane
• Selectable number of lanes per quad from 1 to 16
• Adjustable line rate (in Gb/s)
  • For all supported devices, 0.5 to 13.75 (only up to 12.5 for -1 parts)
  • For supported devices with GT, 0.5 to 28.21 (only up to 25.785 for -1 parts)
• Adjustable Ref Clock selection
  • Clock selections based from chosen line rate
• Supports transceiver type selection
  • Shows the available transceiver types based on the device chosen in the project
• Selectable GT locations
  • Overwritable locations with Xilinx design constraints (XDC)
• Enable bit error ratio tester for debugging live system