AXI4-Lite Register Set

The AXI4-Lite Interface provides a memory mapped interface for all programmable registers within the core. All registers default to the values specified in Page 2 of the core GUI. All other bits default to 0x00000000 on Power-on/Reset unless otherwise noted.

Note: Map overview and full register descriptions are included in Table: Control Register (Address Offset 0x0000) through Table: Generator Global Delay Register (Address Offset 0x140) below.

Table 2-3: AXI4-Lite Address Map
Address Offset	Name	Access Type	Double Buffered	Default Value	Description
0x0000	CONTROL (XVTC_CTL)	R/W	Yes	0	General Control
0x0004	STATUS (XVTC_STATS)	R/WC	No	0	Core/Interrupt Status All Status bits are write-1-to-clear
0x0008	ERROR (XVTC_ERROR)	R/WC	No	0	Additional Status & Error Conditions All Error bits are write-1-to-clear
0x000C	IRQ_ENABLE (XVTC_IER)	R/W	No	0	Interrupt Enable/Disable
0x0010	VERSION (XVTC_VER)	R	N/A	0x06010001	Core Hardware Version
0x0014	ADAPTIVE_SYNC_CTRL	R/W	N/A	0	[0]: Adaptive Sync Enable [1]: Type of Adaptive Sync ⁽¹⁾
0x0018	Stretch Limit (VFP Max)	R/W	N/A	0	Maximum value of the Stretch value which is the maximum front porch value (in pixels) supported based on the maximum frame rate supported in case of adaptive sync ⁽¹⁾
0x0020	DETECTOR ACTIVE_SIZE (XVTC_DASIZE)	R	N/A	0	Horizontal and Vertical Frame Size (without blanking)
0x0024	DETECTOR TIMING_STATUS (XVTC_DTSTAT)	R	N/A	0	Timing Measurement Status
0x0028	DETECTOR ENCODING (XVTC_DFENC)	R	N/A	0	Frame encoding
0x002C	DETECTOR POLARITY (XVTC_DPOL)	R	N/A	0	Blank, Sync polarities
0x0030	DETECTOR HSIZE (XVTC_DHSIZE)	R	N/A	0	Horizontal Frame Size (with blanking)
0x0034	DETECTOR VSIZE (XVTC_DVSIZE)	R	N/A	0	Vertical Frame Size (with blanking)
0x0038	DETECTOR HSYNC (XVTC_DHSYNC)	R	N/A	0	Start and end cycle index of HSync
0x003C	DETECTOR F0_VBLANK_H (XVTC_DVBHOFF)	R	N/A	0	Start and end cycle index of VBlank for field 0.
0x0040	DETECTOR F0_VSYNC_V (XVTC_DVSYNC)	R	N/A	0	Start and end line index of VSync for field 0.
0x0044	DETECTOR F0_VSYNC_H (XVTC_DVSHOFF)	R	N/A	0	Start and end cycle index of VSync for field 0.
0x0048	DETECTOR F1_VBLANK_H (XVTC_DVBHOFF_F1)	R	N/A	0	Start and end cycle index of VBlank for field 1.
0x004C	DETECTOR F1_VSYNC_V (XVTC_DVSYNC_F1)	R	N/A	0	Start and end line index of VSync for field 1.
0x0050	DETECTOR F1_VSYNC_H (XVTC_DVSHOFF_F1)	R	N/A	0	Start and end cycle index of VSync for field 1.
0x006 0	GENERATOR ACTIVE_SIZE (XVTC_GASIZE_F0)	R/W	Yes	Specified via GUI	Horizontal and Vertical Frame Size (without blanking) for field 0.
0x0064	GENERATOR TIMING_STATUS (XVTC_GTSTAT)	R	No	Specified via GUI	Timing Measurement Status
0x0068	GENERATOR ENCODING (XVTC_GFENC)	R/W	Yes	Specified via GUI	Frame encoding
0x006C	GENERATOR POLARITY (XVTC_GPOL)	R/W	Yes	Specified via GUI	Blank, Sync polarities
0x007 0	GENERATOR HSIZE (XVTC_GHSIZE)	R/W	Yes	Specified via GUI	Horizontal Frame Size (with blanking)
0x0074	GENERATOR VSIZE (XVTC_GVSIZE)	R/W	Yes	Specified via GUI	Vertical Frame Size (with blanking)
0x0078	GENERATOR HSYNC (XVTC_GHSYNC)	R/W	Yes	Specified via GUI	Start and end cycle index of HSync
0x007C	GENERATOR F0_VBLANK_H (XVTC_GVBHOFF)	R/W	Yes	Specified via GUI	Start and end cycle index of VBlank for field 0.
0x008 0	GENERATOR F0_VSYNC_V (XVTC_GVSYNC)	R/W	Yes	Specified via GUI	Start and end line index of VSync for field 0.
0x0084	GENERATOR F0_VSYNC_H (XVTC_GVSHOFF)	R/W	Yes	Specified via GUI	Start and end cycle index of VSync for field 0.
0x0088	GENERATOR F1_VBLANK_H (XVTC_GVBHOFF_F1)	R/W	Yes	Specified via GUI	Start and end cycle index of VBlank for field 1.
0x008C	GENERATOR F1_VSYNC_V (XVTC_GVSYNC_F1)	R/W	Yes	Specified via GUI	Start and end line index of VSync for field 1.
0x0090	GENERATOR F1_VSYNC_H (XVTC_GVSHOFF_F1)	R/W	Yes	Specified via GUI	Start and end cycle index of VSync for field 1.
0x0094	GENERATOR ACTIVE_SIZE (XVTC_GASIZE_F1)	R/W	Yes	Specified via GUI	Horizontal and Vertical Frame size for field 1.
0x0095 … 0x00FC	RESERVED	R	N/A	0	RESERVED
0x0100 … 0x013c	FRAME SYNC 0 - 15 CONFIG (XVTC_FS00 - XVTC_FS15)	R/W	Yes	0	Horizontal start clock and vertical start line of Frame Sync 0 - 15
0x0140	GENERATOR GLOBAL DELAY (XVTC_GGD)	R/W	Yes	0	Horizontal cycle and vertical line delay of generator.
Notes: 1. The adaptive sync feature is supported only in HDMI and DP sub-systems.

Table 2-4: Control Register (Address Offset 0x0000)
0x0000	CONTROL	Read/Write
Name	Bits	Description
SW_RESET	31	Core reset. Writing a '1' resets the core. This bit automatically clears when reset complete.
FSYNC_RESET	30	Frame Sync Core reset. Writing a '1' resets the core after the start of the next input frame. This bit automatically clears when reset complete.
RESERVED	29:27	Reserved
FIELD_ID_POL_SRC	26	Field ID Polarity Source Select 0: selects generated polarity from detection register (0x002c) 1: selects generated polarity from generators register (0x006c)
ACTIVE_CHROMA_POL_SRC	25	Active Chroma Polarity Source Select 0: selects generated polarity from detection register (0x002c) 1: selects generated polarity from generator register (0x006c)
ACTIVE_VIDEO_POL_SRC	24	Active Video Polarity Source Select 0: selects generated polarity from detection register (0x002c) 1: selects generated polarity from generator register (0x006c)
HSYNC_POL_SRC	23	Horizontal Sync Polarity Source Select 0: selects generated polarity from detection register (0x002c) 1: selects generated polarity from generator register (0x006c)
VSYNC_POL_SRC	22	Vertical Sync Polarity Source Select 0: selects generated polarity from detection register (0x002c) 1: selects generated polarity from generator register (0x006c)
HBLANK_POL_SRC	21	Horizontal Blank Polarity Source Select 0: selects generated polarity from detection register (0x002c) 1: selects generated polarity from generator register (0x006c)
VBLANK_POL_SRC	20	Vertical Blank Polarity Source Select .0: selects generated polarity from detection register (0x002c) 1: selects generated polarity from generator register (0x006c)
RESERVED	19	RESERVED
CHROMA_SRC	18	Generator Chroma Polarity and Encoding Source Select 0: selects Polarity and encoding from detection registers 0x0028 and 0x002C. 1: selects Polarity and encoding from generator registers 0x0068 and 0x006C.
VBLANK_HOFF_SRC	17	Generator Vertical Blank Offset Source Select 0: selects F0_VBLANK_HSTART from detection register (0x003c) selects F0_VBLANK_HEND from detection register (0x003c) 1: selects F0_VBLANK_HSTART from generator register (0x007c) selects F0_VBLANK_HEND from generator register (0x007c)
VSYNC_END_SRC	16	Generator Vertical Sync End Source Select 0: selects F0_VSYNC_HEND from detection register (0x0044) selects F0_VSYNC_VEND from detection register (0x0040) 1: selects F0_VSYNC_HEND from generator register (0x0084) selects F0_VSYNC_VEND from generator register (0x0080)
VSYNC_START_SRC	15	Generator Vertical Sync Start Source Select 0: selects F0_VSYNC_HSTART from detection register (0x0044) selects F0_VSYNC_VSTART from detection register (0x0040) 1: selects F0_VSYNC_HSTART from generator register (0x0084) selects F0_VSYNC_VSTART from generator register (0x0080)
ACTIVE_VSIZE_SRC	14	Generator Vertical Active Size Source Select 0: selects ACTIVE_VSIZE from detection register (0x0020) 1: selects ACTIVE_VSIZE from generator register (0x0060)
FRAME_VSIZE_SRC	13	Generator Vertical Frame Size Source Select 0: selects FRAME_VSIZE from detection register (0x0034) 1: selects FRAME_VSIZE from generator register (0x0074)
RESERVED	12	Reserved
HSYNC_END_SRC	11	Generator Horizontal Sync End Source Select 0: selects HSYNC_END from detection register (0x0038) 1: selects HSYNC_END from generator register (0x0078)
HSYNC_START_SRC	10	Generator Horizontal Sync Start Source Select 0: selects HSYNC_START from detection register (0x0038) 1: selects HSYNC_START from generator register (0x0078)
ACTIVE_HSIZE_SRC	9	Generator Horizontal Active Size Source Select 0: selects ACTIVE_HSIZE from detection register (0x0020) 1: selects ACTIVE_HSIZE from generator register (0x0060)
FRAME_HSIZE_SRC	8	Generator Horizontal Frame Size Source Select 0: selects FRAME_HSIZE from detection register (0x0030) 1: selects FRAME_HSIZE from generator register (0x0070)
RESERVED	7:6	Reserved
SYNC_ENABLE	5	Generator Synchronization Enable. Enables the generator to synchronize to the Detector or to the fsync_in pin. 1: Generator synchronizes to the Detector or to fsync_in 0: Generator does not synchronize.
RESERVED	4	Reserved
DET_ENABLE	3	Detection Enable. 1: Perform timing signal detection for enabled signals. 0: If SW_ENABLE is '0', No detection will be performed. All 'locked' status bits will be driven Low. SW_ENABLE must be '0' to utilize the DET_ENABLE bit. If SW_ENABLE is '1', both the detector and generator will be enabled.
GEN_ENABLE	2	Generation Enable. 1: Enable hardware to generate output. Set this bit High only after the software has configured the generator registers. 0: If SW_ENABLE is '0', The generation hardware will not generate video timing output signals. SW_ENABLE must be '0' to utilize the DET_ENABLE bit. If SW_ENABLE is '1', both the detector and generator will be enabled.
REG_UPDATE	1	Register Update. Generator and Fsync Registers are double-buffered. 1: Update the Generator and Fsync registers at the start of next frame. 0: Do not update the Generator and Fsync registers.
SW_ENABLE	0	Core Enable. 1: Enable both the Video Timing Generator and Detector. 0: Generator or Detector can be selectively enabled with bits 2 and 3 of the CONTROL register.

The DET_ENABLE bit allows enabling the detector independently from the generator. The internal detector enable is a logical "OR" between the DET_ENABLE and SW_ENABLE bits in the control register. The internal logic that controls the detector sub-core enable is shown in This Figure . The SW_ENABLE bit allows setting one bit to '1' to enable both the detector and the generator. To enable the detector or the generator only, the SW_ENABLE bit must be set to '0' and the detector/generator ENABLE bits (Control Register bits [3:2]) set independently.

Figure 2-5: Detector Internal Enable Logic
X-Ref Target - Figure 2-5

The internal generator enable is a logical "OR" between the GEN_ENABLE and SW_ENABLE bits in the control register. The internal logic that controls the generator sub-core enable is shown in This Figure .

Figure 2-6: Generator Internal Enable Logic
X-Ref Target - Figure 2-6

Table 2-5: Status Register (Address Offset 0x0004)
0x0004	STATUS	Read/Write
Name	Bits	Description
FSYNC	31:16	Frame Synchronization Interrupt Status. Bits 16-31 are set High when frame syncs 0-15 are set respectively.
RESERVED	15:14	Reserved
GEN_ACTIVE_VIDEO	13	Generated Active Video Interrupt Status. Set High during the first cycle the output active video is asserted.
GEN_VBLANK	12	Generated Vertical Blank Interrupt Status. Set High during the first cycle the output vertical blank is asserted.
DET_ACTIVE_VIDEO	11	Detected Active Video Interrupt Status. Set High during the first cycle the input active video is asserted active after lock.
DET_VBLANK	10	Detected Vertical Blank Interrupt Status. Set High during the first cycle the input vertical blank is asserted active after lock.
LOCK_LOSS	9	Loss-of-Lock Status. Set High when any detection signals have lost locked. Signals that have detection disabled will not affect this bit. Check ERROR (0x0008) Register for signal lock status.
LOCK	8	Lock Status. Set High when all detection signals have locked. Signals that have detection disabled will not affect this bit. Check ERROR (0x0008) Register for signal lock status. The detector typically takes from 3 to 5 video frame periods to lock onto the incoming video standard.
RESERVED	7:0	Reserved
Notes: 1. Writing a '1' to a bit in the STATUS register will clear the corresponding interrupt when set. Writing a '1' to a bit that is cleared, will have no effect.

Table 2-6: Error Register (Address Offset 0x0008)
0x0008	ERROR	Read/Write
Name	Bits	Description
RESERVED	31:22	Reserved
ACTIVE_CHROMA_LOCK	21	Active Chroma Lock Status. Set High when the active chroma timing remains unchanged.
ACTIVE_VIDEO_LOCK	20	Active Video Lock Status. Set High when the active video timing remains unchanged.
HSYNC_LOCK	19	Horizontal Sync Lock Status. Set High when the horizontal sync timing remains unchanged.
VSYNC_LOCK	18	Vertical Sync Lock Status. Set High when the vertical sync timing remains unchanged.
HBLANK_LOCK	17	Horizontal Blank Lock Status. Set High when the horizontal blank timing remains unchanged.
VBLANK_LOCK	16	Vertical Blank Lock Status Set High when the vertical blank timing remains Unchanged.
RESERVED	15:0	Reserved
Notes: 1. Writing a '1' to a bit in the ERROR register will clear the corresponding bit when set. Writing a '1' to a bit that is cleared, will have no effect.

Table 2-7: IRQ Enable Register (Address Offset 0x000C)
0x000C	IRQ_ENABLE	Read/Write
Name	Bits	Description
FSYNC	31:16	Frame Synchronization Interrupt Enable
RESERVED	15:14	Reserved
GEN_ACTIVE_VIDEO	13	Generated Active Video Interrupt Enable
GEN_VBLANK	12	Generated Vertical Blank Interrupt Enable
DET_ACTIVE_VIDEO	11	Detected Active Video Interrupt Enable
DET_VBLANK	10	Detected Vertical Blank Interrupt Enable
LOCK_LOSS	9	Loss-of-Lock Interrupt Enable
LOCK	8	Lock Interrupt Enable
RESERVED	7:0	Reserved
Notes: 1. Setting a bit High in the IRQ_ENABLE register enables the corresponding interrupt. Bits that are Low mask the corresponding interrupt from triggering.

Table 2-8: Version Register (Address Offset 0x0010)
0x0010	VERSION	Read
Name	Bits	Description
MAJOR	31:24	Major version as a hexadecimal value (0x00 - 0xFF)
MINOR	23:16	Minor version as a hexadecimal value (0x00 - 0xFF)
REVISION	15:12	Revision as a hexadecimal value (0x0 - 0xF)
PATCH_REVISION	11:8	Core Revision as a single 4-bit hexadecimal value (0x0 - 0xF) Used for patch tracking.
INTERNAL_REVISION	7:0	Internal revision number. Hexadecimal value (0x00 - 0xFF)

Table 2-9: Detector Active Size Register (Address Offset 0x0020)
0x0020	DETECTOR ACTIVE_SIZE	Read
Name	Bits	Description
RESERVED	31:29	Reserved
ACTIVE_VSIZE	28:16	Detected Vertical Active Frame Size. The height of the frame without blanking in number of lines.
RESERVED	15:13	Reserved
ACTIVE_HSIZE	12:0	Detected Horizontal Active Frame Size. The width of the frame without blanking in number of pixels/clocks.

Table 2-10: Detector Timing Status Register (Address Offset 0x0024)
0x0024	DETECTOR TIMING_STATUS	Read
Name	Bits	Description
RESERVED	31:3	Reserved
DET_ACTIVE_VIDEO	2	Detected Active Video Interrupt Status. Set High during the first cycle the input active video is asserted active after lock.
DET_VBLANK	1	Detected Vertical Blank Interrupt Status. Set High during the first cycle the input vertical blank is asserted active after lock.
LOCKED	0	Lock Status. Set High when all detection signals have locked. Signals that have detection disabled will not affect this bit. Check ERROR (0x0008) Register for which signal lock status. The detector typically requires 3 to 5 video frame periods to lock onto the incoming video standard. This bit will not latch the lock status, thus, it shows the real-time status of lock as opposed to the LOCKED bit in the Status Register which must be cleared.

Table 2-11: Detector Encoding Register (Address Offset 0x0028)
0x0028	DETECTOR ENCODING	Read
Name	Bits	Description
RESERVED	31:10	Reserved
CHROMA_PARITY	9:8	Detected Chroma Parity 0: Chroma Active during even active-video lines of frame. Active every pixel of active line 1: Chroma Active during odd active-video lines of frame. Active every pixel of active line 2: Chroma Active during even active video lines of frame. Active every even pixel of active line, inactive every odd pixel 3: Chroma Active during odd active video lines of frame. Active every even pixel of active line, inactive every odd pixel
FIELD_ID_PARITY	7	Detected Field ID Parity 0: Field ID output is currently Low 1: Field ID output is currently High
INTERLACED	6	Detected Progressive/Interlaced 0: Input video format is progressive 1: Input video format is interlaced
RESERVED	5:4	Reserved
VIDEO_FORMAT	3:0	Detected Video Format Denotes when the active_chroma signal is active. 0: YUV 4:2:2 - Active_chroma is active during the same time active_video is active. 1: YUV 4:4:4 - Active_chroma is active during the same time active_video is active. 2: RGB - Active_chroma is active during the same time active_video is active. 3: YUV 4:2:0- Active_chroma is active every other line during the same time active_video is active. See The CHROMA_PARITY bits to control which lines and pixels.

Table 2-12: Detector Polarity Register (Address Offset 0x002C)
0x002C	DETECTOR POLARITY	Read
Name	Bits	Description
RESERVED	31:7	Reserved
FIELD_ID_POL	6	Detected Field ID Polarity 0: Low during Field 0 and High during Field 1 1: High during Field 0 and Low during Field 1
ACTIVE_CHROMA_POL	5	Detected Active Chroma Polarity 0: active-Low Polarity 1: active-High Polarity
ACTIVE_VIDEO_POL	4	Detected Active Video Polarity 0: active-Low Polarity 1: active-High Polarity
HSYNC_POL	3	Detected Horizontal Sync Polarity 0: active-Low Polarity 1: active-High Polarity
VSYNC_POL	2	Detected Vertical Sync Polarity 0: active-Low Polarity 1: active-High Polarity
HBLANK_POL	1	Detected Horizontal Blank Polarity 0: active-Low Polarity 1: active-High Polarity
VBLANK_POL	0	Detected Vertical Blank Polarity 0: active-Low Polarity 1: active-High Polarity

Table 2-13: Detector Horizontal Frame Size Register (Address Offset 0x0030)
0x0030	DETECTOR HSIZE	Read
Name	Bits	Description
RESERVED	31:13	Reserved
FRAME_HSIZE	12:0	Detected Horizontal Frame Size. The width of the frame with blanking in number of pixels/clocks.

Table 2-14: Detector Vertical Frame Size Register (Address Offset 0x0034)
0x0034	DETECTOR VSIZE	Read
Name	Bits	Description
RESERVED	31:29	Reserved
FIELD1_VSIZE	28:16	Detected Vertical Field 1 Size. The height with blanking in number of lines of field 1.
FRAME_VSIZE	12:0	Detected Vertical Frame or Field 0 Size. The height of the frame with blanking in number of lines.

Table 2-15: Detector Horizontal Sync Register (Address Offset 0x0038)
0x0038	DETECTOR HSYNC	Read
Name	Bits	Description
RESERVED	31:29	Reserved
HSYNC_END	28:16	Detected Horizontal Sync End End cycle index of horizontal sync. Denotes the first cycle hsync_in is de-asserted.
RESERVED	15:13	Reserved
HSYNC_START	12:0	Detected Horizontal Sync End Start cycle index of horizontal sync. Denotes the first cycle hsync_in is asserted.

Table 2-16: Detector Frame/Field 0 Vertical Blank Cycle Register (Address Offset 0x003C)
0x003C	DETECTOR F0_VBLANK_H	Read
Name	Bits	Description
RESERVED	31:29	Reserved
F0_VBLANK_HEND	28:16	Detected Vertical Blank Horizontal End End Cycle index of vertical blank. Denotes the first cycle vblank_in is de-asserted.
RESERVED	15:13	Reserved
F0_VBLANK_HSTART	12:0	Detected Vertical Blank Horizontal Start Start Cycle index of vertical blank. Denotes the first cycle vblank_in is asserted.

Table 2-17: Detector Frame/Field 0 Vertical Sync Line Register (Address Offset 0x0040)
0x0040	DETECTOR F0_VSYNC_V	Read
Name	Bits	Description
RESERVED	31:29	Reserved
F0_VSYNC_VEND	28:16	Detected Vertical Sync Vertical End End Line index of vertical sync. Denotes the first line vsync_in is de-asserted.
RESERVED	15:13	Reserved
F0_VSYNC_VSTART	12:0	Detected Vertical Sync Vertical Start Start line index of vertical sync. Denotes the first line vsync_in is asserted.

Table 2-18: Detector Frame/Field 0 Vertical Sync Cycle Register (Address Offset 0x0044)
0x0044	DETECTOR F0_VSYNC_H	Read
Name	Bits	Description
RESERVED	31:29	Reserved
F0_VSYNC_HEND	28:16	Detected Vertical Sync Horizontal End End cycle index of vertical sync. Denotes the first cycle vsync_in is de-asserted.
RESERVED	15:13	Reserved
F0_VSYNC_HSTART	12:0	Detected Vertical Sync Horizontal Start Start cycle index of vertical sync. Denotes the first cycle vsync_in is asserted.

Table 2-19: Detector Field 1 Vertical Blank Cycle Register (Address Offset 0x0048)
0x0048	DETECTOR F1_VBLANK_H	Read
Name	Bits	Description
RESERVED	31:29	Reserved
F1_VBLANK_HEND	28:16	Detected Field 1 Vertical Blank Horizontal End End Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is de-asserted.
RESERVED	15:13	Reserved
F1_VBLANK_HSTART	12:0	Detected Field 1 Vertical Blank Horizontal Start Start Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is asserted.

Table 2-20: Detector Field 1 Vertical Sync Line Register (Address Offset 0x004C)
0x004C	DETECTOR F1_VSYNC_V	Read
Name	Bits	Description
RESERVED	31:29	Reserved
F1_VSYNC_VEND	28:16	Detected Field 1 Vertical Sync Vertical End End Line index of vertical sync for field 1. Denotes the first line vsync_in is de-asserted.
RESERVED	15:13	Reserved
F1_VSYNC_VSTART	12:0	Detected Field 1 Vertical Sync Vertical Start Start line index of vertical sync for field 1. Denotes the first line vsync_in is asserted.

Table 2-21: Detector Field 1 Vertical Sync Cycle Register (Address Offset 0x0050)
0x0050	DETECTOR F1_VSYNC_H	Read
Name	Bits	Description
RESERVED	31:29	Reserved
F1_VSYNC_HEND	28:16	Detected Field 1 Vertical Sync Horizontal End End cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is de-asserted.
RESERVED	15:13	Reserved
F1_VSYNC_HSTART	12:0	Detected Field 1 Vertical Sync Horizontal Start Start cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is asserted.

Table 2-22: Generator Active Size Register for Field 0 (Address Offset 0x0060)
0x0060	GENERATOR ACTIVE_SIZE	Read/Write
Name	Bits	Description
RESERVED	31:29	Reserved
ACTIVE_VSIZE	28:16	Generated Vertical Active Frame Size. The height of the frame without blanking in number of lines.
RESERVED	15:13	Reserved
ACTIVE_HSIZE	12:0	Generated Horizontal Active Frame Size. The width of the frame without blanking in number of cycles ⁽ 1 ) .
Notes: 1. Cycles must be always divisible by pixels per clock. For example, Cycles (Clocks) = Horizontal Resolution/ Pixels per clock.

Table 2-23: Generator Timing Status Register (Address Offset 0x0064)
0x0064	GENERATOR TIMING_STATUS	Read
Name	Bits	Description
RESERVED	31:3	Reserved
GEN_ACTIVE_VIDEO	2	Generated Active Video Interrupt Status. Set High during the first cycle the output active video is asserted.
GEN_VBLANK	1	Generated Vertical Blank Interrupt Status. Set High during the first cycle the output vertical blank is asserted.
RESERVED	0	Reserved

Table 2-24: Generator Encoding Register (Address Offset 0x0068)
0x0068	GENERATOR ENCODING	Read/Write
Name	Bits	Description
RESERVED	31:10	Reserved
CHROMA_PARITY	9:8	Generated Chroma Parity 0: Chroma Active during even active-video lines of frame. Active every pixel of active line 1: Chroma Active during odd active-video lines of frame. Active every pixel of active line 2: Chroma Active during even active video lines of frame. Active every even pixel of active line, inactive every odd pixel 3: Chroma Active during odd active video lines of frame. Active every even pixel of active line, inactive every odd pixel
FIELD_ID_PARITY	7	Generated Field ID Parity 0: Field ID input is currently Low 1: Field ID input is currently High
INTERLACED	6	Generated Progressive/Interlaced 0: Generated video format is progressive 1: Generated video format is interlaced
RESERVED	5:4	Reserved
VIDEO_FORMAT	3:0	Generated Video Format Denotes when the active_chroma signal is active. 0: YUV 4:2:2 - Active_chroma is active during the same time active_video is active. 1: YUV 4:4:4 - Active_chroma is active during the same time active_video is active. 2: RGB - Active_chroma is active during the same time active_video is active. 3: YUV 4:2:0- Active_chroma is active every other line during the same time active_video is active. See The CHROMA_PARITY bits to control which lines and pixels.

Table 2-25: Generator Polarity Register (Address Offset 0x006C)
0x006C	GENERATOR POLARITY	Read/Write
Name	Bits	Description
RESERVED	31:7	Reserved
FIELD_ID_POL	6	Generated Field ID Polarity 0: Low during Field 0 and High during Field 1 1: High during Field 0 and Low during Field 1
ACTIVE_CHROMA_POL	5	Generated Active Chroma Polarity 0: active-Low Polarity 1: active-High Polarity
ACTIVE_VIDEO_POL	4	Generated Active Video Polarity 0: active-Low Polarity 1: active-High Polarity
HSYNC_POL	3	Generated Horizontal Sync Polarity 0: active-Low Polarity 1: active-High Polarity
VSYNC_POL	2	Generated Vertical Sync Polarity 0: active-Low Polarity 1: active-High Polarity
HBLANK_POL	1	Generated Horizontal Blank Polarity 0: active-Low Polarity 1: active-High Polarity
VBLANK_POL	0	Generated Vertical Blank Polarity 0: active-Low Polarity 1: active-High Polarity

Table 2-26: Generator Horizontal Frame Size Register (Address Offset 0x0070)
0x0070	GENERATOR HSIZE	Read/Write
Name	Bits	Description
RESERVED	31:13	Reserved
FRAME_HSIZE	12:0	Generated Horizontal Frame Size. The width of the frame with blanking in number of cycles ⁽ 1 ) .
Notes: 1. Cycles must be always divisible by pixels per clock. For example, Cycles (Clocks) = Horizontal Resolution/ Pixels per clock.

Table 2-27: Generator Vertical Frame Size Register (Address Offset 0x0074)
0x0074	GENERATOR VSIZE	Read/Write
Name	Bits	Description
RESERVED	31:29	Reserved
FIELD1_VSIZE	28:16	Generated Vertical Field 1 Size. The height with blanking in number of lines of field 1.
FRAME_VSIZE	12:0	Generated Vertical Frame Size. The height of the frame with blanking in number of lines.

Table 2-28: Generator Horizontal Sync Register (Address Offset 0x0078)
0x0078	GENERATOR HSYNC	Read/Write
Name	Bits	Description
RESERVED	31:29	Reserved
HSYNC_END	28:16	Generated Horizontal Sync End End cycle index of horizontal sync. Denotes the first cycle hsync_in is de-asserted.
RESERVED	15:13	Reserved
HSYNC_START	12:0	Generated Horizontal Sync End Start cycle index of horizontal sync. Denotes the first cycle hsync_in is asserted.

Table 2-29: Generator Frame/Field 0 Vertical Blank Cycle Register (Address Offset 0x007C)
0x007C	GENERATOR F0_VBLANK_H	Read/Write
Name	Bits	Description
RESERVED	31:29	Reserved
F0_VBLANK_HEND	28:16	Generated Vertical Blank Horizontal End End Cycle index of vertical blank. Denotes the first cycle vblank_in is de-asserted.
RESERVED	15:13	Reserved
F0_VBLANK_HSTART	12:0	Generated Vertical Blank Horizontal Start Start Cycle index of vertical blank. Denotes the first cycle vblank_in is asserted.

Table 2-30: Generator Frame/Field 0 Vertical Sync Line Register (Address Offset 0x0080)
0x0080	GENERATOR F0_VSYNC_V	Read/Write
Name	Bits	Description
RESERVED	31:29	Reserved
F0_VSYNC_VEND	28:16	Generated Vertical Sync Vertical End End Line index of vertical sync. Denotes the first line vsync_in is de-asserted.
RESERVED	15:13	Reserved
F0_VSYNC_VSTART	12:0	Generated Vertical Sync Vertical Start Start line index of vertical sync. Denotes the first line vsync_in is asserted.

Table 2-31: Generator Frame/Field 0 Vertical Sync Cycle Register (Address Offset 0x0084)
0x0084	GENERATOR F0_VSYNC_H	Read/Write
Name	Bits	Description
RESERVED	31:29	Reserved
F0_VSYNC_HEND	28:16	Generated Vertical Sync Horizontal End End cycle index of vertical sync. Denotes the first cycle vsync_in is de-asserted.
RESERVED	15:13	Reserved
F0_VSYNC_HSTART	12:0	Generated Vertical Sync Horizontal Start Start cycle index of vertical sync. Denotes the first cycle vsync_in is asserted.

Table 2-32: Generator Field 1 Vertical Blank Cycle Register (Address Offset 0x0088)
0x0088	GENERATOR F1_VBLANK_H	Read
Name	Bits	Description
RESERVED	31:29	Reserved
F1_VBLANK_HEND	28:16	Generated Field 1 Vertical Blank Horizontal End End Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is de-asserted.
RESERVED	15:13	Reserved
F1_VBLANK_HSTART	12:0	Generated Field 1 Vertical Blank Horizontal Start Start Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is asserted.

Table 2-33: Generator Field 1 Vertical Sync Line Register (Address Offset 0x008C)
0x008C	GENERATOR F1_VSYNC_V	Read
Name	Bits	Description
RESERVED	31:29	Reserved
F1_VSYNC_VEND	28:16	Generated Field 1 Vertical Sync Vertical End End Line index of vertical sync for field 1. Denotes the first line vsync_in is de-asserted.
RESERVED	15:13	Reserved
F1_VSYNC_VSTART	12:0	Generated Field 1 Vertical Sync Vertical Start Start line index of vertical sync for field 1. Denotes the first line vsync_in is asserted.

Table 2-34: Generator Field 1 Vertical Sync Cycle Register (Address Offset 0x0090)
0x0090	GENERATOR F1_VSYNC_H	Read
Name	Bits	Description
RESERVED	31:29	Reserved
F1_VSYNC_HEND	28:16	Generated Field 1 Vertical Sync Horizontal End End cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is de-asserted.
RESERVED	15:13	Reserved
F1_VSYNC_HSTART	12:0	Generated Field 1 Vertical Sync Horizontal Start Start cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is asserted.

Table 2-35: Generator Active Size Register for Field 1 (Address Offset 0x0094)
0x0100	FRAME SYNC 0 CONFIG	Read/Write
Name	Bits	Description
RESERVED	31:29	Reserved
ACTIVE_VSIZE	28:16	Generated Vertical Active Frame Size. The height of the frame without blanking in number of lines.
RESERVED	15:13	Reserved
ACTIVE_HSIZE	12:0	Generated Horizontal Active Frame Size. The width of the frame without blanking in number of cycles ⁽ 1 ) .
Notes: 1. Cycles must be always divisible by pixels per clock. For example, Cycles (Clocks) = Horizontal Resolution/ Pixels per clock.

Table 2-36: Frame Sync 0-15 Configuration Registers (Address Offsets 0x0100 - 0x013C)
0x0100	FRAME SYNC 0 CONFIG	Read/Write
Name	Bits	Description
RESERVED	31:29	Reserved
V_START	28:16	FRAME SYNCHRONIZATION VERTICAL START Vertical line during which the fsync_out[0] output port is asserted active-High. Note: Frame Syncs are not active during the complete line, only in the cycle during which both the V_START and H_START are valid each frame.
RESERVED	15:13	Reserved
H_START	12:0	FRAME SYNCHRONIZATION HORIZONTAL START Horizontal Cycle during which fsync_out[0] output port is asserted active-High

Frame Sync 1-15 Config Registers (address offset 0x0100 - 0x013c) have the same format as the Frame Sync 0 Config Register.

Table 2-37: Generator Global Delay Register (Address Offset 0x140)
0x140	Generator Global Delay	Read/Write
Name	Bits	Description
Reserved	31:29	Reserved
V_DELAY	28:16	GENERATOR VERTICAL DELAY Vertical line offset. This is the number of lines that the generated output will be shifted relative to the detector (input timing). The vertical delay is only available when both the detector and generator are enabled. Can be combined with the H_DELAY.
Reserved	15:13	Reserved
H_DELAY	12:0	GENERATOR HORIZONTAL DELAY Horizontal cycle offset. This is the number of clock cycles that the generated output will be shifted relative to the detector (input timing). The horizontal delay is only available when both the detector and generator are enabled. Can be combined with the V_DELAY.

AXI4-Lite Register Set - 6.2 English

Video Timing Controller Product Guide (PG016)