The AXI4-Lite Interface provides a memory mapped interface for all programmable registers within the core. All registers default to the values specified in Page 2 of the core GUI. All other bits default to 0x00000000 on Power-on/Reset unless otherwise noted.
Note: Map overview and full register descriptions are included in Table: Control Register (Address Offset 0x0000) through Table: Generator Global Delay Register (Address Offset 0x140) below.
Address Offset |
Name |
Access Type |
Double Buffered |
Default Value |
Description |
---|---|---|---|---|---|
0x0000 |
CONTROL (XVTC_CTL) |
R/W |
Yes |
0 |
General Control |
0x0004 |
STATUS (XVTC_STATS) |
R/WC |
No |
0 |
Core/Interrupt Status All Status bits are write-1-to-clear |
0x0008 |
ERROR (XVTC_ERROR) |
R/WC |
No |
0 |
Additional Status & Error Conditions All Error bits are write-1-to-clear |
0x000C |
IRQ_ENABLE (XVTC_IER) |
R/W |
No |
0 |
Interrupt Enable/Disable |
0x0010 |
VERSION (XVTC_VER) |
R |
N/A |
0x06010001 |
Core Hardware Version |
0x0014 |
ADAPTIVE_SYNC_CTRL |
R/W |
N/A |
0 |
[0]: Adaptive Sync Enable [1]: Type of Adaptive Sync (1) |
0x0018 |
Stretch Limit (VFP Max) |
R/W |
N/A |
0 |
Maximum value of the Stretch value which is the maximum front porch value (in pixels) supported based on the maximum frame rate supported in case of adaptive sync (1) |
0x0020 |
DETECTOR ACTIVE_SIZE (XVTC_DASIZE) |
R |
N/A |
0 |
Horizontal and Vertical Frame Size (without blanking) |
0x0024 |
DETECTOR TIMING_STATUS (XVTC_DTSTAT) |
R |
N/A |
0 |
Timing Measurement Status |
0x0028 |
DETECTOR ENCODING (XVTC_DFENC) |
R |
N/A |
0 |
Frame encoding |
0x002C |
DETECTOR POLARITY (XVTC_DPOL) |
R |
N/A |
0 |
Blank, Sync polarities |
0x0030 |
DETECTOR HSIZE (XVTC_DHSIZE) |
R |
N/A |
0 |
Horizontal Frame Size (with blanking) |
0x0034 |
DETECTOR VSIZE (XVTC_DVSIZE) |
R |
N/A |
0 |
Vertical Frame Size (with blanking) |
0x0038 |
DETECTOR HSYNC (XVTC_DHSYNC) |
R |
N/A |
0 |
Start and end cycle index of HSync |
0x003C |
DETECTOR F0_VBLANK_H (XVTC_DVBHOFF) |
R |
N/A |
0 |
Start and end cycle index of VBlank for field 0. |
0x0040 |
DETECTOR F0_VSYNC_V (XVTC_DVSYNC) |
R |
N/A |
0 |
Start and end line index of VSync for field 0. |
0x0044 |
DETECTOR F0_VSYNC_H (XVTC_DVSHOFF) |
R |
N/A |
0 |
Start and end cycle index of VSync for field 0. |
0x0048 |
DETECTOR F1_VBLANK_H (XVTC_DVBHOFF_F1) |
R |
N/A |
0 |
Start and end cycle index of VBlank for field 1. |
0x004C |
DETECTOR F1_VSYNC_V (XVTC_DVSYNC_F1) |
R |
N/A |
0 |
Start and end line index of VSync for field 1. |
0x0050 |
DETECTOR F1_VSYNC_H (XVTC_DVSHOFF_F1) |
R |
N/A |
0 |
Start and end cycle index of VSync for field 1. |
0x006 0 |
GENERATOR ACTIVE_SIZE (XVTC_GASIZE_F0) |
R/W |
Yes |
Specified via GUI |
Horizontal and Vertical Frame Size (without blanking) for field 0. |
0x0064 |
GENERATOR TIMING_STATUS (XVTC_GTSTAT) |
R |
No |
Specified via GUI |
Timing Measurement Status |
0x0068 |
GENERATOR ENCODING (XVTC_GFENC) |
R/W |
Yes |
Specified via GUI |
Frame encoding |
0x006C |
GENERATOR POLARITY (XVTC_GPOL) |
R/W |
Yes |
Specified via GUI |
Blank, Sync polarities |
0x007 0 |
GENERATOR HSIZE (XVTC_GHSIZE) |
R/W |
Yes |
Specified via GUI |
Horizontal Frame Size (with blanking) |
0x0074 |
GENERATOR VSIZE (XVTC_GVSIZE) |
R/W |
Yes |
Specified via GUI |
Vertical Frame Size (with blanking) |
0x0078 |
GENERATOR HSYNC (XVTC_GHSYNC) |
R/W |
Yes |
Specified via GUI |
Start and end cycle index of HSync |
0x007C |
GENERATOR F0_VBLANK_H (XVTC_GVBHOFF) |
R/W |
Yes |
Specified via GUI |
Start and end cycle index of VBlank for field 0. |
0x008 0 |
GENERATOR F0_VSYNC_V (XVTC_GVSYNC) |
R/W |
Yes |
Specified via GUI |
Start and end line index of VSync for field 0. |
0x0084 |
GENERATOR F0_VSYNC_H (XVTC_GVSHOFF) |
R/W |
Yes |
Specified via GUI |
Start and end cycle index of VSync for field 0. |
0x0088 |
GENERATOR F1_VBLANK_H (XVTC_GVBHOFF_F1) |
R/W |
Yes |
Specified via GUI |
Start and end cycle index of VBlank for field 1. |
0x008C |
GENERATOR F1_VSYNC_V (XVTC_GVSYNC_F1) |
R/W |
Yes |
Specified via GUI |
Start and end line index of VSync for field 1. |
0x0090 |
GENERATOR F1_VSYNC_H (XVTC_GVSHOFF_F1) |
R/W |
Yes |
Specified via GUI |
Start and end cycle index of VSync for field 1. |
0x0094 |
GENERATOR ACTIVE_SIZE (XVTC_GASIZE_F1) |
R/W |
Yes |
Specified via GUI |
Horizontal and Vertical Frame size for field 1. |
0x0095 … 0x00FC |
RESERVED |
R |
N/A |
0 |
RESERVED |
0x0100 … 0x013c |
FRAME SYNC 0 - 15 CONFIG (XVTC_FS00 - XVTC_FS15) |
R/W |
Yes |
0 |
Horizontal start clock and vertical start line of Frame Sync 0 - 15 |
0x0140 |
GENERATOR GLOBAL DELAY (XVTC_GGD) |
R/W |
Yes |
0 |
Horizontal cycle and vertical line delay of generator. |
Notes: 1. The adaptive sync feature is supported only in HDMI and DP sub-systems. |
The DET_ENABLE bit allows enabling the detector independently from the generator. The internal detector enable is a logical "OR" between the DET_ENABLE and SW_ENABLE bits in the control register. The internal logic that controls the detector sub-core enable is shown in This Figure . The SW_ENABLE bit allows setting one bit to '1' to enable both the detector and the generator. To enable the detector or the generator only, the SW_ENABLE bit must be set to '0' and the detector/generator ENABLE bits (Control Register bits [3:2]) set independently.
The internal generator enable is a logical "OR" between the GEN_ENABLE and SW_ENABLE bits in the control register. The internal logic that controls the generator sub-core enable is shown in This Figure .
0x0004 |
STATUS |
Read/Write |
---|---|---|
Name |
Bits |
Description |
FSYNC |
31:16 |
Frame Synchronization Interrupt Status. Bits 16-31 are set High when frame syncs
|
RESERVED |
15:14 |
Reserved |
GEN_ACTIVE_VIDEO |
13 |
Generated Active Video Interrupt Status. Set High during the first cycle the output active video is asserted. |
GEN_VBLANK |
12 |
Generated Vertical Blank Interrupt Status. Set High during the first cycle the output vertical blank is asserted. |
DET_ACTIVE_VIDEO |
11 |
Detected Active Video Interrupt Status. Set High during the first cycle the input active video is asserted active after lock. |
DET_VBLANK |
10 |
Detected Vertical Blank Interrupt Status. Set High during the first cycle the input vertical blank is asserted active after lock. |
LOCK_LOSS |
9 |
Loss-of-Lock Status. Set High when any detection signals have lost locked. Signals that have detection disabled will not affect this bit.
|
LOCK |
8 |
Lock Status. Set High when all detection signals have locked. Signals that have detection disabled will not affect this bit.
|
RESERVED |
7:0 |
Reserved |
Notes: 1. Writing a '1' to a bit in the STATUS register will clear the corresponding interrupt when set. Writing a '1' to a bit that is cleared, will have no effect. |
0x0008 |
ERROR |
Read/Write |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:22 |
Reserved |
ACTIVE_CHROMA_LOCK |
21 |
Active Chroma Lock Status. Set High when the active chroma timing remains unchanged. |
ACTIVE_VIDEO_LOCK |
20 |
Active Video Lock Status. Set High when the active video timing remains unchanged. |
HSYNC_LOCK |
19 |
Horizontal Sync Lock Status. Set High when the horizontal sync timing remains unchanged. |
VSYNC_LOCK |
18 |
Vertical Sync Lock Status. Set High when the vertical sync timing remains unchanged. |
HBLANK_LOCK |
17 |
Horizontal Blank Lock Status. Set High when the horizontal blank timing remains unchanged. |
VBLANK_LOCK |
16 |
Vertical Blank Lock Status Set High when the vertical blank timing remains Unchanged. |
RESERVED |
15:0 |
Reserved |
Notes: 1. Writing a '1' to a bit in the ERROR register will clear the corresponding bit when set. Writing a '1' to a bit that is cleared, will have no effect. |
0x000C |
IRQ_ENABLE |
Read/Write |
---|---|---|
Name |
Bits |
Description |
FSYNC |
31:16 |
Frame Synchronization Interrupt Enable |
RESERVED |
15:14 |
Reserved |
GEN_ACTIVE_VIDEO |
13 |
Generated Active Video Interrupt Enable |
GEN_VBLANK |
12 |
Generated Vertical Blank Interrupt Enable |
DET_ACTIVE_VIDEO |
11 |
Detected Active Video Interrupt Enable |
DET_VBLANK |
10 |
Detected Vertical Blank Interrupt Enable |
LOCK_LOSS |
9 |
Loss-of-Lock Interrupt Enable |
LOCK |
8 |
Lock Interrupt Enable |
RESERVED |
7:0 |
Reserved |
Notes: 1. Setting a bit High in the IRQ_ENABLE register enables the corresponding interrupt. Bits that are Low mask the corresponding interrupt from triggering. |
0x0010 |
VERSION |
Read |
---|---|---|
Name |
Bits |
Description |
MAJOR |
31:24 |
Major version as a hexadecimal value (0x00 - 0xFF) |
MINOR |
23:16 |
Minor version as a hexadecimal value (0x00 - 0xFF) |
REVISION |
15:12 |
Revision as a hexadecimal value (0x0 - 0xF) |
PATCH_REVISION |
11:8 |
Core Revision as a single 4-bit hexadecimal value (0x0 - 0xF) Used for patch tracking. |
INTERNAL_REVISION |
7:0 |
Internal revision number. Hexadecimal value (0x00 - 0xFF) |
0x0020 |
DETECTOR ACTIVE_SIZE |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
ACTIVE_VSIZE |
28:16 |
Detected Vertical Active Frame Size.
|
RESERVED |
15:13 |
Reserved |
ACTIVE_HSIZE |
12:0 |
Detected Horizontal Active Frame Size.
|
0x0024 |
DETECTOR TIMING_STATUS |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:3 |
Reserved |
DET_ACTIVE_VIDEO |
2 |
Detected Active Video Interrupt Status. Set High during the first cycle the input active video is asserted active after lock. |
DET_VBLANK |
1 |
Detected Vertical Blank Interrupt Status. Set High during the first cycle the input vertical blank is asserted active after lock. |
LOCKED |
0 |
Lock Status. Set High when all detection signals have locked. Signals that have detection disabled will not affect this bit. Check ERROR (0x0008) Register for which signal lock status. The detector typically requires 3 to 5 video frame periods to lock onto the incoming video standard. This bit will not latch the lock status, thus, it shows the real-time status of lock as opposed to the LOCKED bit in the Status Register which must be cleared. |
0x0028 |
DETECTOR ENCODING |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:10 |
Reserved |
CHROMA_PARITY |
9:8 |
Detected Chroma Parity
|
FIELD_ID_PARITY |
7 |
Detected Field ID Parity 0: Field ID output is currently Low 1: Field ID output is currently High |
INTERLACED |
6 |
Detected Progressive/Interlaced 0: Input video format is progressive 1: Input video format is interlaced |
RESERVED |
5:4 |
Reserved |
VIDEO_FORMAT |
3:0 |
Detected Video Format Denotes when the active_chroma signal is active.
|
0x002C |
DETECTOR POLARITY |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:7 |
Reserved |
FIELD_ID_POL |
6 |
Detected Field ID Polarity 0: Low during Field 0 and High during Field 1 1: High during Field 0 and Low during Field 1 |
ACTIVE_CHROMA_POL |
5 |
Detected Active Chroma Polarity
|
ACTIVE_VIDEO_POL |
4 |
Detected Active Video Polarity
|
HSYNC_POL |
3 |
Detected Horizontal Sync Polarity
|
VSYNC_POL |
2 |
Detected Vertical Sync Polarity
|
HBLANK_POL |
1 |
Detected Horizontal Blank Polarity
|
VBLANK_POL |
0 |
Detected Vertical Blank Polarity
|
0x0030 |
DETECTOR HSIZE |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:13 |
Reserved |
FRAME_HSIZE |
12:0 |
Detected Horizontal Frame Size. The width of the frame with blanking in number of pixels/clocks. |
0x0034 |
DETECTOR VSIZE |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
FIELD1_VSIZE |
28:16 |
Detected Vertical Field 1 Size. The height with blanking in number of lines of field 1. |
FRAME_VSIZE |
12:0 |
Detected Vertical Frame or Field 0 Size. The height of the frame with blanking in number of lines. |
0x0038 |
DETECTOR HSYNC |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
HSYNC_END |
28:16 |
Detected Horizontal Sync End
|
RESERVED |
15:13 |
Reserved |
HSYNC_START |
12:0 |
Detected Horizontal Sync End
|
0x003C |
DETECTOR F0_VBLANK_H |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F0_VBLANK_HEND |
28:16 |
Detected Vertical Blank Horizontal End
|
RESERVED |
15:13 |
Reserved |
F0_VBLANK_HSTART |
12:0 |
Detected Vertical Blank Horizontal Start
|
0x0040 |
DETECTOR F0_VSYNC_V |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F0_VSYNC_VEND |
28:16 |
Detected Vertical Sync Vertical End
|
RESERVED |
15:13 |
Reserved |
F0_VSYNC_VSTART |
12:0 |
Detected Vertical Sync Vertical Start
|
0x0044 |
DETECTOR F0_VSYNC_H |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F0_VSYNC_HEND |
28:16 |
Detected Vertical Sync Horizontal End
|
RESERVED |
15:13 |
Reserved |
F0_VSYNC_HSTART |
12:0 |
Detected Vertical Sync Horizontal Start
|
0x0048 |
DETECTOR F1_VBLANK_H |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F1_VBLANK_HEND |
28:16 |
Detected Field 1 Vertical Blank Horizontal End End Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is de-asserted. |
RESERVED |
15:13 |
Reserved |
F1_VBLANK_HSTART |
12:0 |
Detected Field 1 Vertical Blank Horizontal Start Start Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is asserted. |
0x004C |
DETECTOR F1_VSYNC_V |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F1_VSYNC_VEND |
28:16 |
Detected Field 1 Vertical Sync Vertical End End Line index of vertical sync for field 1. Denotes the first line vsync_in is de-asserted. |
RESERVED |
15:13 |
Reserved |
F1_VSYNC_VSTART |
12:0 |
Detected Field 1 Vertical Sync Vertical Start Start line index of vertical sync for field 1. Denotes the first line vsync_in is asserted. |
0x0050 |
DETECTOR F1_VSYNC_H |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F1_VSYNC_HEND |
28:16 |
Detected Field 1 Vertical Sync Horizontal End End cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is de-asserted. |
RESERVED |
15:13 |
Reserved |
F1_VSYNC_HSTART |
12:0 |
Detected Field 1 Vertical Sync Horizontal Start Start cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is asserted. |
0x0064 |
GENERATOR TIMING_STATUS |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:3 |
Reserved |
GEN_ACTIVE_VIDEO |
2 |
Generated Active Video Interrupt Status. Set High during the first cycle the output active video is asserted. |
GEN_VBLANK |
1 |
Generated Vertical Blank Interrupt Status. Set High during the first cycle the output vertical blank is asserted. |
RESERVED |
0 |
Reserved |
0x0068 |
GENERATOR ENCODING |
Read/Write |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:10 |
Reserved |
CHROMA_PARITY |
9:8 |
Generated Chroma Parity
|
FIELD_ID_PARITY |
7 |
Generated Field ID Parity 0: Field ID input is currently Low 1: Field ID input is currently High |
INTERLACED |
6 |
Generated Progressive/Interlaced 0: Generated video format is progressive 1: Generated video format is interlaced |
RESERVED |
5:4 |
Reserved |
VIDEO_FORMAT |
3:0 |
Generated Video Format Denotes when the active_chroma signal is active.
|
0x006C |
GENERATOR POLARITY |
Read/Write |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:7 |
Reserved |
FIELD_ID_POL |
6 |
Generated Field ID Polarity 0: Low during Field 0 and High during Field 1 1: High during Field 0 and Low during Field 1 |
ACTIVE_CHROMA_POL |
5 |
Generated Active Chroma Polarity
|
ACTIVE_VIDEO_POL |
4 |
Generated Active Video Polarity
|
HSYNC_POL |
3 |
Generated Horizontal Sync Polarity
|
VSYNC_POL |
2 |
Generated Vertical Sync Polarity
|
HBLANK_POL |
1 |
Generated Horizontal Blank Polarity
|
VBLANK_POL |
0 |
Generated Vertical Blank Polarity
|
0x0074 |
GENERATOR VSIZE |
Read/Write |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
FIELD1_VSIZE |
28:16 |
Generated Vertical Field 1 Size. The height with blanking in number of lines of field 1. |
FRAME_VSIZE |
12:0 |
Generated Vertical Frame Size. The height of the frame with blanking in number of lines. |
0x0078 |
GENERATOR HSYNC |
Read/Write |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
HSYNC_END |
28:16 |
Generated Horizontal Sync End
|
RESERVED |
15:13 |
Reserved |
HSYNC_START |
12:0 |
Generated Horizontal Sync End
|
0x007C |
GENERATOR F0_VBLANK_H |
Read/Write |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F0_VBLANK_HEND |
28:16 |
Generated Vertical Blank Horizontal End
|
RESERVED |
15:13 |
Reserved |
F0_VBLANK_HSTART |
12:0 |
Generated Vertical Blank Horizontal Start
|
0x0080 |
GENERATOR F0_VSYNC_V |
Read/Write |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F0_VSYNC_VEND |
28:16 |
Generated Vertical Sync Vertical End
|
RESERVED |
15:13 |
Reserved |
F0_VSYNC_VSTART |
12:0 |
Generated Vertical Sync Vertical Start
|
0x0084 |
GENERATOR F0_VSYNC_H |
Read/Write |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F0_VSYNC_HEND |
28:16 |
Generated Vertical Sync Horizontal End
|
RESERVED |
15:13 |
Reserved |
F0_VSYNC_HSTART |
12:0 |
Generated Vertical Sync Horizontal Start
|
0x0088 |
GENERATOR F1_VBLANK_H |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F1_VBLANK_HEND |
28:16 |
Generated Field 1 Vertical Blank Horizontal End End Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is de-asserted. |
RESERVED |
15:13 |
Reserved |
F1_VBLANK_HSTART |
12:0 |
Generated Field 1 Vertical Blank Horizontal Start Start Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is asserted. |
0x008C |
GENERATOR F1_VSYNC_V |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F1_VSYNC_VEND |
28:16 |
Generated Field 1 Vertical Sync Vertical End End Line index of vertical sync for field 1. Denotes the first line vsync_in is de-asserted. |
RESERVED |
15:13 |
Reserved |
F1_VSYNC_VSTART |
12:0 |
Generated Field 1 Vertical Sync Vertical Start Start line index of vertical sync for field 1. Denotes the first line vsync_in is asserted. |
0x0090 |
GENERATOR F1_VSYNC_H |
Read |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
F1_VSYNC_HEND |
28:16 |
Generated Field 1 Vertical Sync Horizontal End End cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is de-asserted. |
RESERVED |
15:13 |
Reserved |
F1_VSYNC_HSTART |
12:0 |
Generated Field 1 Vertical Sync Horizontal Start Start cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is asserted. |
0x0100 |
FRAME SYNC 0 CONFIG |
Read/Write |
---|---|---|
Name |
Bits |
Description |
RESERVED |
31:29 |
Reserved |
V_START |
28:16 |
FRAME SYNCHRONIZATION VERTICAL START
|
RESERVED |
15:13 |
Reserved |
H_START |
12:0 |
FRAME SYNCHRONIZATION HORIZONTAL START
|
Frame Sync 1-15 Config Registers (address offset 0x0100 - 0x013c) have the same format as the Frame Sync 0 Config Register.