The Video Timing Controller core has multiple enable options: the CLKEN pin (hardware clock enable), and the software enable option provided via the AXI4-Lite control interface (when present).
The CLKEN pin cannot ensure synchronization internally to video timing processing therefore de-asserting CLKEN for extended periods of time may lead to generating incomplete frames or lengthening the period needed to detect incoming video frame timing.
The CLKEN pin facilitates:
• Multi-cycle path designs (High speed clock division without clock gating),
• Standby operation of subsystems to save on power
• Hardware controlled bring-up of system components