Features - 6.2 English

Video Timing Controller Product Guide (PG016)

Document ID
Release Date
6.2 English

Support for progressive or interlaced video frame sizes up to 16,384 x 16,384

Direct regeneration of output timing signals with independent timing and polarity inversion

Automatic detection and generation of horizontal and vertical video timing signals

Support for multiple combinations of blanking or synchronization signals

Automatic detection of input video control signal polarities

Support for detection and generation of horizontal delay of vertical blank/sync

Programmable output video signal polarities

Generation of up to 16 additional independent output frame synchronization signals

Optional AXI4-Lite processor interface

High number of interrupts and status registers for easy system control and integration

LogiCORE IP Facts Table

Core Specifics

Supported Device Family ( 1 )

UltraScale+™ Families

UltraScale™ Architecture

Versal™ ACAP

Zynq ® -7000 SoC , 7 Series FPGAs

Supported User Interfaces

AXI4-Lite ( 2 )


Performance and Resource Utilization

web page

Provided with Core

Design Files

Encrypted RTL

Example Design

Not Provided

Test Bench


Constraints File


Simulation Models

Encrypted RTL, VHDL, or Verilog Structural

Supported Software Drivers


Tested Design Flows ( 3 )

Design Entry Tools

Vivado ® Design Suite


For supported simulators, see the
Xilinx Design Tools: Release Notes Guide .

Synthesis Tools

Vivado Synthesis


Release Notes and Known Issues

Master Answer Record: 54541

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page

1. For a complete listing of supported devices, see the Vivado IP Catalog.

2. Refer to the Video IP: AXI Feature Adoption section of AXI Reference Guide [Ref 8] .

3. For the supported versions of third-party tools, see the
Xilinx Design Tools: Release Notes Guide .