Interrupts - 6.2 English

Video Timing Controller Product Guide (PG016)

Document ID
PG016
Release Date
2022-10-19
Version
6.2 English

The Video Timing Controller has an active-High interrupt output port named "irq". This output is set High when an interrupt occurs and set Low when the interrupt event has been cleared. The Video Timing Controller also contains three 32-bit registers for configuring and reporting status of interrupts: the Interrupt Status/Clear, the Interrupt Enable and the Interrupt Clear Registers. A logical AND is performed on the Interrupt Enable Register and the Interrupt Status Register to set the interrupt output High. The Interrupt Clear Register is used to clear the Interrupt Status Register. Writing a '1' to a bit in the Interrupt Status Register clears the corresponding interrupt when set. Writing a '1' to a bit that is cleared, will have no effect.