RESETn - 6.2 English

Video Timing Controller Product Guide (PG016)

Document ID
PG016
Release Date
2022-10-19
Version
6.2 English

The Video Timing Controller core has two reset sources: the RESETn pin (hardware reset), and the software reset provided via the AXI4-Lite control interface (when present). The software reset is available via the control register at address offset 0x0000, bit 31.

IMPORTANT: RESETn is not synchronized internally to the video timing processing. De-asserting RESETn while frame timing is being process can lead to incomplete frames (from the generator).

The external reset pulse needs to be held for at least 32 CLK cycles to reset the core. The RESETn signal only resets the video timing interfaces and processing of the core. The AXI4-Lite interface is unaffected by the RESETn signal to allow the video timing processing core to be reset without halting the AXI4-Lite interface. However, if the RESETn is asserted Low during an AXI4-Lite register read or write, the AXI4-Lite interface asserts the slave error response (0x2) for all addresses.

IMPORTANT: When a system with multiple-clocks and corresponding reset signals are being reset, the reset generator has to ensure all signals are asserted/de-asserted long enough so that all interfaces and clock-domains are correctly reinitialized.