Required Constraints - 6.2 English

Video Timing Controller Product Guide (PG016)

Document ID
PG016
Release Date
2022-10-19
Version
6.2 English

The only constraints required are clock frequency constraints for the video clock, clk , and the AXI4-Lite clock, s_axi_aclk . Paths between the two clock domains should be constrained with a max_delay constraint and use the datapathonly flag, causing setup and hold checks to be ignored for signals that cross clock domains. These constraints are provided in the XDC constraints file included with the core.