Revision History - 6.2 English

Video Timing Controller Product Guide (PG016)

Document ID
PG016
Release Date
2022-10-19
Version
6.2 English

The following table shows the revision history for this document.

Date

Version

Revision

10/19/2022

6.2

General updates.

02/26/2021

6.2

Added Versal ACAP support.

10/30/2019

6.2

Updated the Video Mode parameter to configure only standard resolutions from GUI when AXI4-LITE interface is not used. For non-standard resolutions, the Custom option must be selected.

05/22/2019

6.1

Updated Table: AXI4-Lite Address Map .

02/12/2019

6.1

Added new register for Field1 Active lines for all interlaced modes.

10/04/2017

6.1

Updated the fsync_in Pin section. Updated Control Signals and Timing section to describe dual/quad pixel mode.

11/18/2015

6.1

Added UltraScale+ support.

10/01/2014

6.1

Removed Application Software Development appendix.

12/18/2013

6.1

Added UltraScale Architecture support. Added interlaced video support

10/02/2013

6.0

Synch document version with core version. Updated Constraints.

03/20/2013

4.0

Updated for core version to v6.0. Updated Debugging appendix. Removed ISE chapters. Added new det_clken , and gen_clken pins, new Clocking pins, Resets, DET_ENABLE and GEN_ENABLE bits.

10/16/2012

3.1

Updated for core version and ISE v14.3 and Vivado v2012.3. Added Vivado test bench and constraints.

07/25/2012

3.0

Updated for core version. Added Vivado information.

4/24/2012

2.0

Updated for core version. Added Zynq-7000 devices, deprecated GPP interface.

10/19/2011

1.0

Initial Xilinx release of Product Guide, replacing DS857.