The AXI4-Lite interface uses the S_AXI_ACLK pin as its clock source. The CLK pin is not shared between the AXI4-Lite and video timing interfaces. The Video Timing Controller core contains clock-domain crossing logic between the CLK (video timing) and S_AXI_ACLK (AXI4-Lite) clock domains. The core automatically ensures that the AXI4-Lite transactions completes even if the video processing is stalled with RESETn , CLKEN or with the video clock not running.
Even though the core ensures that AXI-Lite transactions complete, it is better design to avoid this situation if possible and only access the AXI-Lite interface when a video clock is present.