S_AXI_ARESETn - 6.2 English

Video Timing Controller Product Guide (PG016)

Document ID
PG016
Release Date
2022-10-19
Version
6.2 English

The S_AXI_ARESETn signal is synchronous to the S_AXI_ACLK clock domain, but is internally synchronized to the CLK clock domain. The S_AXI_ARESETn signal resets the entire core including the AXI4-Lite and video timing interfaces.