The clk Pin - 6.2 English

Video Timing Controller Product Guide (PG016)

Document ID
PG016
Release Date
2022-10-19
Version
6.2 English

The Video Timing interfaces must be synchronous to the core clock signal clk . All Video Timing interface input signals are sampled on the rising edge of clk . All Video Timing output signal changes occur after the rising edge of clk . If the clk signal is not running, the AXI4-Lite interface asserts the slave error response (0x2) for all addresses. The clken pin is an active-High, synchronous clock-enable input pertaining to Video Timing interfaces. Setting clken Low (de-asserted) halts the operation of the core despite rising edges on the clk pin. Internal states are maintained, and output signal levels are held until clken is asserted again. When clken is de-asserted, core inputs are not sampled, except resetn , which supersedes clken . This clock must be running for AXI4-Lite registers to be read and/or written, since all core registers reside within the core clock domain. This clock enable must be asserted High for AXI4-Lite registers to be read and/or written, since all core registers reside within the core clock domain. If the clock enable is deasserted, the AXI4-Lite interface asserts the slave error response (0x2) for all addresses.