The resetn Pin - 6.2 English

Video Timing Controller Product Guide (PG016)

Document ID
PG016
Release Date
2022-10-19
Version
6.2 English

The resetn pin is an active-Low, synchronous reset input pertaining to only Video Timing interfaces. resetn supersedes clken , and when set to 0, the core resets at the next rising edge of clk even if clken is de-asserted. The resetn signal must be synchronous to the clk and must be held Low for a minimum of 32 clock cycles of the slowest clock. This reset must be asserted High for AXI4-Lite registers to be read and/or written, since all core registers reside within the core clock domain. If the reset is asserted Low, the AXI4-Lite interface asserts the slave error response (0x2) for all addresses.