Use Model - 6.2 English

Video Timing Controller Product Guide (PG016)

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6.2 English

This section illustrates likely usage scenarios for the Xilinx® Video Timing Controller core.

Figure 3-8: Example Video Timing Controller Use Model

X-Ref Target - Figure 3-8


This Figure shows four features of the Video Timing Controller being utilized in a video system:

Detection of the source video frame timing

Generation of video timing signals

Generation of two Frame Syncs to control the Video Processors

Connection to a Host Processor via the AXI4-Lite interface

To detect the timing of the source video, the timing signals are connected to the Video Timing Controller Detection Module. Both the timing and the signal polarity of the timing signals are captured and easily read by the host processor.

Video timing signals are generated to control a AXI4-Stream to Video-Out module and an external display. The timing of these output signals is controlled by the host processor. The Video Timing Controller can be configured in real-time to replicate the source video format or to slightly change the format on the output, for example, in cases where the input signals are positive polarity yet the display requires negative polarity synchronization signals. The Video Timing Controller can also be reconfigured in real-time to output a completely different format from the input source.

Two Frame Sync outputs are generated to control Video Processor 1 and Video Processor 2. These outputs could be used to control when Video Processor 2 starts processing relative to when Video Processor 1 starts processing. These Frame Syncs can be reconfigured in real-time as well.

The Video Timing Controller is connected to a Host Processor in this example. The AXI4-Lite Interface allows for easy connection between status/control registers and the host processor. In addition, the Video Timing Controller interrupt output can also be used to synchronize the software with hardware events.

If the video system requires that only complete video frames are sent from the Video-In To AXI4-Stream core, then the Video Timing Controller must be configured to drive the axis_enable input with bit 8 of the INTC_IF bus. This bus must be enabled with the "Include INTC Interface".

Figure 3-9: Video Timing Controller Generator Synchronization Use Model

X-Ref Target - Figure 3-9


This Figure shows the ability of the Video Timing Controller to synchronize the timing generator to an incoming frame sync, vertical sync or vertical blank signal. This is useful to generate timing signals that are not present. For example, if blank signals can be generated from sync signals. Also, this allows the timing generator to synchronize to a separate timing generator

In this example, the bottom timing generator can be synchronized to the top timing controller, a separate vsync or separate vblank signal. This is controlled by the mux "Select" signal.

IMPORTANT: The timing generator can be offset from the input by configuring the Generator Global Delay Register (Address Offset 0x140)].

Once the fsync_in input is selected, the pixel or line offset delay of the synchronized generator can be configured with the Generator Global Delay Register.