The following parameters, registers, and ports are hidden as it is not required for most use cases. However, these parameters and associated features can be enabled by entering the following mentioned command in the Tcl Console in the Vivado Integrated Design Environment (IDE).
Any hidden parameter mentioned in Table: Parameters can be enabled in the Vivado design tools using the following command.
set_property -dict [list CONFIG.param_name {1}] [get_ips axi_vdma_xyz]
Where axi_vdma_xyz is the component name in the Vivado design tools.
To enable all debug options and ports, use the following command.
set_property -dict [list CONFIG.c_enable_all {1}] [get_ips axi_vdma_xyz]
Where axi_vdma_xyz is the component name the Vivado design tools.
To enable the any hidden parameter mentioned in Table: Parameters in the IP integrator, use the following command.
set_property -dict [list CONFIG.param_name {1}] [get_bd_cells axi_vdma_xyz]
Where axi_vdma_xyz is the component name in the IP integrator.
Note: You need to regenerate output products for the core after setting the parameter using the Tcl Console command in the Vivado design tools.
Table 4-2: Parameters
|
Parameter
|
Default
Value
|
Description
|
|
C_MM2S_GENLOCK_NUM_MASTERS
|
1 (Range 1 to 16)
|
Specifies the number of Genlock Masters that Genlock Slave can synchronize in the Read channel. MM2S_DMACR[11:8] in Genlock Slave should be programmed to the Genlock Master number to which Genlock Slave should get synchronized to. mm2s_frame_ptr_in
([C_MM2S_GENLOCK_NUM_MASTERS*6]–1:0)
|
|
C_S2MM_GENLOCK_NUM_MASTERS
|
1 (Range 1 to 16)
|
Specifies the number of Genlock Masters that Genlock Slave can synchronize in the Read channel. S2MM_DMACR[11:8] in Genlock Slave should be programmed to the Genlock Master number to which Genlock Slave should get synchronized to s2mm_frame_ptr_in
([C_S2MM_GENLOCK_NUM_MASTERS*6]–1:0)
|
|
C_ENABLE_S2MM_FRM_COUNTER
|
1
|
1 – Allows programming of Frame Counter (S2MM_VDMACR[23:16]), Frame Count Interrupt Enable (S2MM_VDMACR[12]), and Frame Count Enable(S2MM_VDMACR[4]).
Channel counts incoming frames and reports the frame counter status in S2MM_VDMASR[23:16]. Interrupt can be enabled by setting S2MM_VDMACR[12].
If S2MM_VDMACR[4] is also set, the channel halts after transferring the S2MM_VDMACR[23:16] number of frames.
|
|
C_ENABLE_S2MM_DELAY_COUNTER
|
1
|
1 – Allows programming of Delay Counter (S2MM_VDMACR[31:24]) and Delay Count Interrupt Enable (S2MM_VDMACR[13]). When S2MM_VDMACR[13] is set to 1, the AXI VDMA timer starts incrementing after receiving fsync and compares it with values programmed in S2MM_VDMACR[31:24] and generates an interrupt when it matches. Timer resets with the subsequent start of packet. The Timer status is reported in S2MM_VDMASR[31:24].
|
|
C_ENABLE_S2MM_FRMSTR_REG
|
0
|
1 – Enables S2MM_FRMSTORE (0x48) register. This allows the frame buffers numbers to be modified for the write channel.
|
|
C_ENABLE_S2MM_STS_REG
|
0
|
1 – Enables FRMPTR_STS (24h), S2MM_VSIZE_STATUS (F0h), and S2MM_HSIZE_STATUS (F4h). These registers can be used for debugging purposes.
|
|
C_ENABLE_S2MM_FSYNC_OUT
|
0
|
1 – Enables the s2mm_fsync_out output port.
This signal asserts High for one s_axis_s2mm_aclk cycle with each frame boundary.
|
|
C_ENABLE_S2MM_PARAM_UPDT
|
0
|
1 – Enables the s2mm_prmtr_update output port. This signal indicates that new programmed video parameters (start address, stride, hsize, vsize) take effect on next frame. This signal is asserted for one s_axis_s2mm_aclk cycle coincident with s2mm_fsync_out.
|
|
C_ENABLE_S2MM_BUF_FULL
|
0
|
1 – Enables s2mm_buffer_full, s2mm_buffer_almost_full output ports and enables S2MM_THRESHOLD (0x4C) register.
|
|
C_ENABLE_S2MM_RST_OUT
|
0
|
1 – Enables s2mm_prmry_reset_out_n output port (Active-Low Primary S2MM Reset Out)
|
|
C_ENABLE_MM2S_FRM_COUNTER
|
1
|
1 – Allows programming of Frame Counter (MM2S_VDMACR[23:16]), Frame Count Interrupt Enable (MM2S_VDMACR[12]) and Frame Count Enable (MM2S_VDMACR[4]). The channel counts outgoing frames and reports the frame counter status in MM2S_VDMASR[23:16]. Interrupt can be enabled by setting MM2S_VDMACR[12].
If MM2S_VDMACR[4] is also set, the channel halts after transferring MM2S_VDMACR[23:16] number of frames.
|
|
C_ENABLE_MM2S_DELAY_COUNTER
|
1
|
1 – Allows programming of Delay Counter (MM2S_VDMACR[31:24]) and Delay Count Interrupt Enable (MM2S_VDMACR[13]). When MM2S_VDMACR[13] is set to 1, the AXI VDMA timer starts incrementing after receiving fsync and compares it with values programmed in MM2S_VDMACR[31:24] and generates an interrupt when it matches. Timer resets with subsequent start of packet. Timer status is reported in MM2S_VDMASR[31:24].
|
|
C_ENABLE_MM2S_FRMSTR_REG
|
0
|
1 – Enables MM2S_FRMSTORE (0x18) register. This allows frame buffers numbers to be modified for read channel.
|
|
C_ENABLE_TSTVEC
|
0
|
1 – Enables axi_vdma_tstvec(63:0) output debug port. This is reserved for Xilinx internal debug purposes.
|
|
c_enable_mm2s_fsync_out
|
0
|
1 – Enables mm2s_fsync_out output port. This signal asserts High for one m_axis_mm2s_aclk cycle with each frame boundary.
|
|
C_ENABLE_MM2S_PARAM_UPDT
|
0
|
1 – Enables mm2s_prmtr_update output port. This signal indicates that new programmed video parameters (start address, stride, hsize, vsize) take effect on the next frame. This signal is asserted for one m_axis_mm2s_aclk cycle coincident with mm2s_fsync_out.
|
|
C_ENABLE_MM2S_BUF_EMPTY
|
0
|
1 – Enables mm2s_buffer_empty, mm2s_buffer_almost_empty output ports and enables the MM2S_Threshold (0x1C) register.
|
|
C_ENABLE_MM2S_RST_OUT
|
0
|
1 – Enables mm2s_prmry_reset_out_n output port (Active-Low Primary MM2S Reset Out).
|
|
C_ENABLE_ALL
|
0
|
1 – Enables all the debug options mentioned in this table.
|