Enables or disables the MM2S Data Realignment Engine. When checked, the Data Realignment Engine is enabled and allows data realignment to the byte (8 bits) level on the MM2S Memory Map datapath.
When disabled, the Start Address must be aligned to multiples of the read memory map data width bytes. Also Horizontal Size and Stride must be specified in multiples of read memory map data width bytes. For example, if read memory map data width = 32, data is aligned if the Start Address at word offsets(32-bit offset), that is, 0x0, 0x4, 0x8, 0xC, and so on. Horizontal Size is 0x4, 0x8, 0xC and so on. Stride is 0x4, 0x8, 0xC, and so on.
IMPORTANT: Having an unaligned Start Address, HSize, and/or Stride when Allow Unaligned Transfers is unchecked will result in undefined behavior.
Note: The Data Realignment Engine only supports AXI4-Stream data width settings of 64-bits and less.