AXI VDMA provides two clocking modes of operation: asynchronous and synchronous. In async mode VDMA control, MM2S and S2MM Primary datapaths can all run asynchronously from each other. Checking Enable Asynchronous Mode in the Vivado IDE enables this mode and creates five clock domains.
•AXI4-Lite clock domain clocked by s_axi_lite_aclk
•mm2s clock domain on the memory map side clocked by m_axi_mm2s_aclk
•s2mm clock domain on the memory map side clocked by m_axi_s2mm_aclk
•s2mm clock domain on the streaming side clocked by s_axis_s2mm_aclk
•mm2s clock domain on the streaming side clocked by m_axis_mm2s_aclk
In asynchronous mode, s_axi_lite_aclk clock must have a lower frequency than both m_axi_mm2s_aclk and m_axi_s2mm_aclk clocks.
IMPORTANT: Make sure the memory map side clock frequency is equal to or greater than the streaming side clock frequency to achieve required performance.
In synchronous mode, all logic runs in a single clock domain. The signals m_axi_mm2s_aclk, m_axi_s2mm_aclk, m_axis_mm2s_aclk, and s_axis_s2mm_aclk must be tied to the same source otherwise undefined results occur.
The s_axi_lite_aclk can be connected to a slower clock.