AXI VDMA is compliant to AXI4 on both the memory and streaming side. Any AXI compliant IP can be connected to the core.
Generate the core using the Vivado® Design Suite. See Customizing and Generating the Core.
The core is delivered through the Vivado Design Suite with an HDL example design built around the core, allowing the functionality of the core to be demonstrated using either a simulation package or in hardware, if placed on a suitable board. For details about the Vivado Design Suite example design, see Example Design.
Also see Designing High-Performance Video Systems in 7 Series FPGAs with the AXI Interconnect (XAPP741) [Ref 3], AXI VDMA Reference Design (XAPP742) [Ref 4], AXI Multi-Ported Memory Controller (XAPP739) [Ref 9], and Designing High-Performance Video Systems with the AXI Interconnect (XAPP740) [Ref 10] for various system configuration using AXI VDMA.