Following are common issues that you can encounter:
1.AXI VDMA works, but the bottom few lines are not proper.
Answer: Most of these issues are attributed to the wrong hsize and vsize programming in AXI VDMA. Double-check programmed values and check if fsync signals are connected and fsync period is maintained properly.
2.AXI VDMA locks up.
Answer: The following registers are implemented to help debug the failures:
Bits 7(SOFEarlyErr), 8(EOLEarlyErr), 11(SOFLateErr) and 15(EOLLateErr) of offset 0x34h to identify error occurrence in S2MM path
3.Per VDMA park pointer register read, VDMA channel is not moving to the next frame buffer.
Answer: VDMA park ptr register latches the frame_number value when any (line/frame) error happens. After the error bits are cleared, this register continuously updates the working frame numbers.
4.When the VDMA system is re-initialized through software (or after a soft reset), horizontal shift is observed onscreen.
Answer: This could be related to the system reset release sequence and programming issues. You need to make sure all FIFOs in the datapath are flushed and the VDMA trigger (vsize) is programmed at the end of the initialization sequence.
5.Channel does not come out from reset.
Answer: Check that all clocks related to the VDMA channel have proper connectivity and are running.
6.The AXI VDMA core does not give expected performance.
Answer: Make sure the Memory Map side clock is equal or greater than the Streaming side Clock.
7.Core violates AXI4 protocol (example: ARVALID/AWVALID/WVALID toggles without receiving ARREADY/AWREADY/WREADY from interconnect.)
Answer: Ensure that the system clock connectivity is correct for the VDMA and AXI4 interconnect, that is, the VDMA datapath memory map clock and the corresponding AXI4 Interconnect port clock are tied to the same source.
8.S2MM channel does not transfer any data on the memory side and after a few stream transactions s_axis_s2mm_tready goes Low.
Answer: Ensure that s_axis_s2mm_tkeep is tied to 1 when the Streaming Master IP does not support it.
9.TREADY remains Low.
Answer: This can happen if you are not meeting alignment constraints when Allow Unaligned Transfers is disabled while generating the core. In this case, the start address must be aligned to multiples of the memory map data width bytes. HSize and Stride must be specified in multiples of the memory map data width bytes. For example, if memory map data width = 32, data is aligned if the Start Address at word offsets (32-bit offset), that is, 0x0, 0x4, 0x8, 0xC, and so on. Horizontal Size is 0x4, 0x8, 0xC and so on. Stride is 0x4, 0x8, 0xC, and so on.
10.When you bring up the core and read the status registers for the first time, you are seeing several errors that do not go away.
Answer: Frame size errors are very common at startup because partial frames can be sent to the VDMA at power-up. The VDMA will not halt in this situation, but errors in the status registers will persist until explicitly cleared (R/WC). Before reading the status register for the first time, clear it by writing 0xffffffff. If the errors persist, refer to the other sections of the documentation to continue debugging specific errors.
11.Core outputs too many or not enough frames.
Answer: The rate of frames is controlled by 2 factors. The maximum throughput of the AXI busses and the FSYNC control. If the VDMA is outputting frames too quickly or not quickly enough, check that the FSYNC settings are correct and that the throughput is not too high for the system.
12.See Frame Pointers Gray Code Outputs to enable vsize and hsize counters for debugging purposes.