Latency - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID
PG020
Release Date
2022-06-08
Version
6.3 English

Table: AXI VDMA Latency shows the AXI VDMA core latency cycles measured on write (s2mm) and read (mm2s) paths. It does not include system dependent latency or throttling.

Table 2-2:      AXI VDMA Latency

Description

Clocks

Read (MM2S) Channel

 

Frame Sync out to AXI4 Address Valid

14

AXI4 Read Valid to AXI4-Stream Data Valid

4

Current Frame AXI4-Stream TLAST to Next Frame Sync out

8

Write (S2MM) Channel

 

AXI4-Stream Data Valid to AXI4 Write Address Valid

14

m_axi_s2mm_awvalild and m_axi_s2mm_awready=1 to m_axi_s2mm_wvalid

2

Current AXI4 Write Last to next Frame Sync out

11