MM2S Vertical Size (MM2S_VSIZE – Offset 0x50) - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID
PG020
Release Date
2022-06-08
Version
6.3 English

The vertical size register has a dual purpose: first to hold the number of vertical lines, and second to be the mechanism for starting an MM2S transfer. If MM2S_VDMACR.RS = 1, a write to this register transfers the video parameters and start addresses to an internal register block for VDMA controller use. This register must be written last for a particular channel.

Figure 2-13:      MM2S VSIZE Register

X-Ref Target - Figure 2-13

pg020_Desc_vsize_x12335.jpg

 

Table 2-15:      MM2S VSIZE Register Details

Bits

Field Name

Default Value

Access Type

Description

31–13

Reserved

0h

RO

Writing to these bits has no effect, and they are always read as zeros.

12–0

Vertical Size

(Lines)

0h

R/W

Indicates the vertical size in lines of the video data to transfer.

Note:   Writing a value of zero in this field causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.