Clocking - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2022-04-27
Version
7.1 English

There are four clock inputs:

m_axi_mm2s_aclk for MM2S interface

m_axi_s2mm_aclk for S2MM interface

s_axi_lite_aclk for AXI4-Lite control interface

m_axi_sg_clk for Scatter Gather Interface

AXI DMA provides two clocking modes of operation: asynchronous and synchronous. Setting Enable Asynchronous Clocks enables asynchronous mode and creates four clock domains. This allows high-performance users to run the primary datapaths at a higher clock rate than the DMA control (for example, AXI4-Lite interface, SG Engine, DMA Controller) helping in FPGA placement and timing.

In synchronous mode, all logic runs in a single clock domain. m_axi_sg_aclk, m_axi_mm2s_aclk and m_axi_s2mm_aclk must be tied to the same source, the s_axi_lite_aclk can be connected to a slower clock. In asynchronous mode, clocks can be run asynchronously, however s_axi_lite_aclk must be less than or equal to m_axi_sg_aclk and m_axi_sg_aclk must be less than or equal to the slower of m_axi_mm2s_aclk or m_axi_s2mm_aclk .

The relationship between signal sets and their corresponding clocks in asynchronous mode is shown in Table: Asynchronous Mode Clock Distribution .

Table 3-1: Asynchronous Mode Clock Distribution

Clock Source

I/O Ports (Scatter Gather Enabled)

I/O Ports (Scatter Gather Disabled)

s_axi_lite_aclk

All s_axi_lite_* Signals

mm2s_introut

s2mm_introut

axi_resetn

All s_axi_lite_* Signals

mm2s_introut

s2mm_introut

axi_resetn

m_axi_sg_aclk

All m_axi_sg_* Signals

N/A

m_axi_mm2s_aclk

All m_axi_mm2s_* Signals

All m_axis_mm2s_* Signals

mm2s_prmry_reset_out_n

mm2s_cntrl_reset_out_n

All m_axi_mm2s_* Signals

All m_axis_mm2s_* Signals

mm2s_prmry_reset_out_n

m_axi_s2mm_aclk

All m_axi_s2mm_* Signals

All s_axis_s2mm_* Signals

s2mm_prmry_reset_out_n

s2mm_sts_reset_out_n

All m_axi_s2mm_* Signals

All s_axis_s2mm_* Signals

s2mm_prmry_reset_out_n