• AXI4 compliant
• Optional Scatter/Gather Direct Memory Access (DMA) support
• AXI4 data width support of 32, 64, 128, 256, 512 and 1,024 bits
• AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512 and 1,024 bits
• Optional Keyhole support
• Optional Data Re-Alignment support for streaming data widths up to 512 bits
• Optional AXI Control and Status Streams
• Optional Micro DMA Support
• Support for up to 64-bit addressing
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LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family (1) |
Versal® ACAP, UltraScale+™ UltraScale™ Zynq®-7000 SoC, Xilinx 7 series FPGAs |
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Supported User Interfaces |
AXI4, AXI4-Lite, AXI4-Stream |
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Resources |
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Provided with Core |
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Design Files |
VHDL |
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Example Design |
VHDL |
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Test Bench |
VHDL |
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Constraints File |
Delivered with IP Generation |
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Supported S/W Drivers (2) |
Standalone and Linux |
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Tested Design Flows (3) |
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Design Entry |
Vivado Design Suite |
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Simulation |
For supported simulators, see the
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Synthesis |
Vivado Synthesis |
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Support |
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(1) For a complete list of supported devices, see the Vivado IP catalog.
(2)
Standalone driver information can be found in the Software Development Kit (SDK) installation directory. See xilinx_drivers.htm in
doc/xilinx_drivers.htm.
(3)
For the supported versions of the tools, see the
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