Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues.
Some of the common problems encountered and possible solutions follow.
• Internal Error/Error bits set in the Status register
° Internal error will be set when BTT specified in the descriptor is 0.
° SG internal error will be set if the fetched BD is a completed BD.
° Other error bits like Decode Error or Slave Error would also be set based on the response from Interconnect or Slave.
You are reading data from a location, but the data does not seem to be in order.
Verify if the start address location is aligned or unaligned. If it is not aligned, ensure that the DRE is enabled while configuring DMA.
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