Latency and Throughput

Latency and Throughput - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

Document ID

PG021

Release Date

2022-04-27

Version

7.1 English

Table: AXI DMA Latency Numbers and Table: AXI DMA Throughput Numbers(1) describe the latency and throughput for the AXI DMA. The tables provide performance information for a typical configuration. The throughput test consisted of transferring 10,000 bytes on the MM2S and S2MM side.

Throughput is measured from completion of descriptor fetching (DMACR.Idle = 1) to frame count interrupt assertion.

Table 2-1: AXI DMA Latency Numbers
Description	Clocks
MM2S Channel
Tail Descriptor write to m_axi_sg_arvalid	10
m_axi_sg_arvalid to m_axi_mm2s_arvalid	28
m_axi_mm2s_arvalid to m_axis_mm2s_tvalid	6
S2MM Channel
Tail Descriptor write to m_axi_sg_arvalid	10
s_axis_s2mm_tvalid to m_axi_s2mm_awvalid	39

Table 2-2: AXI DMA Throughput Numbers ⁽¹⁾
Channel	Clock Frequency (MHz)	Bytes Transferred	Total Throughput (MB/s)	Percent of Theoretical
MM2S ⁽²⁾	100	10,000	399.04	99.76
S2MM ⁽³⁾	100	10,000	298.59	74.64
Notes: 1. The preceding figures are measured with the default IP configuration. 2. The MM2S throughput is measured between the first arvalid on Memory Map side to the tlast on streaming side. 3. The S2MM throughput is measured between the first tvalid on streaming side to last wlast on the Memory Map side.