MM2S (TX) Descriptor - 7.1 English

Figure 2-40: TX Descriptor
X-Ref Target - Figure 2-40

Table 2-41: TX Descriptor Fields
Address Space Offset	Name	Description
00h	NXTDESC	Bits 5:0 – Reserved Bits 31:6 – Next Descriptor Pointer
04h	NXTDESC MSB	Provides the upper 32 bits of the next descriptor pointer. Applicable when AXI DMA is configured for an address space greater than 32.
08h	BUFFER_ADDRESS	Bits 31:0 – Buffer Address Provides the location of the data to transfer from Memory Map to Stream. The address should be aligned to the Memory Map data width.
0Ch	BUFFER_ADDRESS	Provides the upper 32 bits of buffer address. This is applicable only when AXI DMA is configured for an address space greater than 32.
		Multichannel Control bits. Bits 4:0 – TDEST provides routing information for the data stream. TDEST values are static for the entire packet. TDEST values provided in the TX descriptor field are presented on TDEST signals of streaming side.
		• Bits 7:5 – Reserved
		• Bits 12:8 – TID: Provides a stream identifier. TID values are static for entire packet. TID values provided in the TX descriptor field are presented on TID signals of the streaming side.
		• Bits 15:13 – Reserved
		• Bits 19:16 – TUSER: Sideband signals used for user-defined information. TUSER values are static for entire packet. TUSER values provided in the TX descriptor field are presented on TUSER signals of streaming side.
10h	MC_CTL	• Bits 23:20 – Reserved
		• Bits 27:24 – ARCACHE: Cache type. This signal provides additional information about the cacheable characteristics of the transfer. See the AMBA® AXI and ACE Protocol Specification [Ref 3] for a different decoding mechanism. ARCACHE values from TX descriptor are presented on ARCACHE [3:0] bus during address cycle. Default value of this field is 0011.
		• Bits 31:28 – ARUSER: Sideband signals used for user-defined information. ARUSER values from TX descriptor are presented on ARUSER [3:0]. ARUSER values and their interpretations are user-defined. You can keep ARUSER static for the entire packet by programming the same values in all the descriptors within a chain.
14h	STRIDE_VSIZE	• Bits 15:0 – Stride Control. It is the address distance between the first address of successive “horizontal” reads. Reads will start at the Buffer Address and read HSIZE bytes, then skip STRIDE-HSIZE addresses and read HSIZE bytes, and so on. This continues until VSIZE lines have been read. On AXI4-Stream this is transmitted out on the m_axis_mm2s_ interface as one contiguous packet and is terminated with a single assertion of TLAST on the last data beat of the transfer. • Bits 18:16 – Reserved • Bits 31:19 – Number of “horizontal lines” for stride access. Can represent two-dimensional video data or the size of a 2-D matrix. This is the number of transfers, each HSIZE bytes long, that are expected to be transmitted for each packet.
18h	HSIZE	• Bits 15:0 – Number of bytes to transfer in each “horizontal line” from successive contiguous byte addresses. Can represent a portion of a video line or a portion of a matrix row when the matrix is read in row major order. • Bits 25:16 – Reserved • Bit 26 – TXEOP – End of packet flag. It indicates the buffer associated with this descriptor is transmitted last. This flag is set by the CPU. 0 – Not end of packet. 1 – End of packet • Bit 27 – TXSOP – Start of packet flag. It indicates the buffer associated with this descriptor is transmitted first. This flag is set by the CPU. 0 – Not start of packet. 1 – Start of packet • Bits 31:28–Reserved
1Ch	MC_STS	Multichannel Status bits. • Bits 27:0 – Reserved • Bit 28 – IE – DMA Internal Error due to under-run or over-run conditions. 0 – No DMA Internal Errors 1 – DMA Internal Error detected. DMA Engine halts. • Bit 29 – SE – DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. 0 – No DMA Slave Errors 1 – DMA Slave Error detected. DMA Engine halts • Bit 30 – DE – DMA Decode Error. This error occurs if the address request is to an invalid address. 0 – No DMA Decode Errors 1 – DMA Decode Error detected. DMA Engine halts • Bit 31 – Cmp – Completed. This indicates to the software that the DMA engine has completed the transfer. 0 – Descriptor not completed 1 – Descriptor completed
Notes: 1. The ARCACHE, ARUSER values are important from the AXI read perspective. These values should be specified in the descriptor as needed. For normal operation ARCACHE should be set to 0011 while ARUSER can be set to 0000. 2. A value of 0 on VSIZE is illegal and results in the multichannel DMA not functioning as expected.