MM2S_LENGTH (MM2S DMA Transfer Length Register

MM2S_LENGTH (MM2S DMA Transfer Length Register — Offset 28h) - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

Document ID

PG021

Release Date

2022-04-27

Version

7.1 English

This register provides the number of bytes to read from system memory and transfer to MM2S AXI4-Stream.

Figure 2-10: MM2S_LENGTH Register
X-Ref Target - Figure 2-10

Table 2-14: MM2S_LENGTH Register Details
Bits	Field Name	Default Value	Access Type	Description
25 ⁽¹⁾ to 0	Length	zeros	R/W	Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.
31 to 26	Reserved	0	RO	Writing to these bits has no effect and they are always read as zeros.
Notes: 1. Width of Length field determined by Buffer Length Register Width parameter. Minimum width is 8 bits (7 to 0) and maximum width is 26 bits (25 to 0).