MM2S_SA (MM2S DMA Source Address Register – Offset 18h)

MM2S_SA (MM2S DMA Source Address Register – Offset 18h) - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

Document ID

PG021

Release Date

2022-04-27

Version

7.1 English

This register provides the Source Address for reading system memory for the Memory Map to Stream DMA transfer.

Figure 2-8: MM2S_SA Register
X-Ref Target - Figure 2-8

Table 2-12: MM2S_SA Register Details
Bits	Field Name	Default Value	Access Type	Description
31 to 0	Source Address	zeros	R/W	Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel. Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.