The AXI DMA core register space for Scatter/Gather Mode is shown in Table: Scatter / Gather Mode Register Address Map . The AXI DMA core register space for Direct Register mode is shown in Table: Direct Register Mode Register Address Map . The AXI DMA registers are memory-mapped into non-cacheable memory space. This memory space must be aligned on an AXI word (32-bit) boundary.
Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (* _wdata ) signal, and is not impacted by the AXI Write Data Strobe (* _wstrb ) signal. For a Write, both the AXI Write Address Valid (* _awvalid ) and AXI Write Data Valid (* _wvalid ) signals should be asserted together.