The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
04/27/2022 |
7.1 |
• Updated Performance section • Updated Scatter Gather Descriptor section |
|
06/14/2019 |
7.1 |
• Updated Table: MM2S_DMASR Register Details and Table: S2MM_DMASR Register Details . • Updated This Figure , This Figure , and This Figure . • Added Enable Single AXI4 Data Interface section. |
|
04/04/2018 |
7.1 |
Added support for 64 MB data transfer. |
|
10/04/2017 |
7.1 |
• Added Documentation Navigator and Design Hubs to this appendix. • Added Automotive Applications Disclaimer. • Updated Data Re-Alignment Engine support to 512 bits (was 64 bits). |
|
10/05/2016 |
7.1 |
• Added a note about the AXI4-Lite write access register to the beginning of the Register Space section. • Added the. • Updated S2MM description. |
|
11/18/2015 |
7.1 |
Added support for UltraScale+ families. |
|
04/01/2015 |
7.1 |
• Fixed link to master answer record. • Added support for 64-bit addressing. |
|
04/02/2014 |
7.1 |
• Added information about the Air Traffic Generator. • Added information about optional Micro DMA. • Added axi_dma_tstvec to I/O signals. |
|
12/18/2013 |
7.1 |
Added UltraScale™ architecture support. |
|
10/02/2013 |
7.1 |
• Added example design. • Added Cyclic BD Enable. • Modified Bits 26 and 27 of the S2MM_CONTROL register. • Updated screen displays. • Added IP integrator information. • Added Enable Micro DMA option. |
|
03/20/2013 |
7.0 |
• Revision number advanced to 7.0 to align with core version number 7.0. • Updated for Vivado Design Suite support and core version 7.0 • Updated Debugging appendix. • Removed one screen capture and updated another in Chapter 4. • Removed ISE®, CORE Generator™, Virtex®-6, and Spartan®-6 material. • Removed Design Parameters and AXI DMA System Configuration sections from Chapter 3. |
|
12/18/2012 |
3.2 |
• Updated for 14.4/2012.4 support and core version 6.03a. • Updated Debugging appendix. • Updated screen captures in Chapter 4. • Replaced Figure 1-1. • Updated devices in Table 2-1, System Performance. • Updated resource numbers in Tables 2-4, 2-5, and 2-6. • Removed Interconnect Parameters and Allowable Parameter Combinations sections. • Updated Output Generation sections in Chapters 4and 7. |
|
10/16/2012 |
3.1 |
Updated for 14.3/2012.3 support. Document cleanup |
|
07/25/2012 |
3.0 |
Summary of Core Changes • Added Vivado tools support and Zynq®-7000 support |
|
04/24/2012 |
2.0 |
Summary of Core Changes • Added multichannel support • Added 2-D transactions support • Added keyhole support • Added Cache and User controls for AXI memory side Interface |
|
10/19/2011 |
1.0 |
Initial Xilinx release. |