This register provides the Current Descriptor Pointer for the Stream to Memory Map DMA Scatter Gather Descriptor Management.
|
X-Ref Target - Figure 2-14 
|
|
Bits |
Field Name |
Default Value |
Access Type |
Description |
|---|---|---|---|---|
|
5 to 0 (Offset 0x38) |
Reserved |
0 |
RO |
Writing to these bits has no effect and they are always read as zeros. |
|
31 to 6 |
Current Descriptor Pointer |
zeros |
R/W (RO) |
Indicates the pointer of the current Buffer Descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing to the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor. When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on. On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error. Note: The register can only be written to by the CPU when the DMA Engine is halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Buffer Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. |