This register provides the upper 32 bits of Destination Address for writing to system memory for the Stream to Memory Map to DMA transfer. This is used only when DMA is configured for address space greater than 32.
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X-Ref Target - Figure 2-19 
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|
Bits |
Field Name |
Default Value |
Access Type |
Description |
|---|---|---|---|---|
|
31 to 0 |
Destination Address |
zeros |
R/W |
Indicates the MSB 32 bits of the destination address the AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel. Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned. |