SG_CTL (Scatter/Gather User and Cache Control Register—Offset 2Ch)

SG_CTL (Scatter/Gather User and Cache Control Register—Offset 2Ch) - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

Document ID

PG021

Release Date

2022-04-27

Version

7.1 English

This register is available only when DMA is configured in multichannel mode.

Figure 2-11: SG_CTL Register
X-Ref Target - Figure 2-11

Table 2-15: SG_CTL Register Details
Bits	Field Name	Default Value	Access Type	Description
3 to 0	SG_CACHE	0011b	R/W	Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.
7 to 4	Reserved	0	RO	Writing to these bits has no effect and they are always read as zeros.
11 to 8	SG_USER	0	R/W	Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.