The AXI DMA core is designed to be connected through the AXI Interconnect in the user system. A typical MicroBlaze™ processor configuration is shown in This Figure . The system microprocessor has access to the AXI DMA through the AXI4-Lite interface. An integrated Scatter/Gather Engine fetches buffer descriptors from system memory which then coordinates primary data transfers between AXI IP and DDRx. Optional control and status streams provide packet-associated information, such as checksum offload control/status, to and from an Ethernet based IP. The dual interrupt output of the AXI DMA core is routed to the System Interrupt Controller.
The AXI DMA core can also be connected to a user system other than with an Ethernet-based AXI IP. Control and status streams are optional and can be used with Ethernet based IP cores only.
Note: In the absence of any setup (that is, before it is programmed to run), AXI DMA will pull the s_axis_s2mm_tready signal Low after taking in four beats of streaming data. This will throttle the input data stream. To have a minimum amount of throttling, ensure that the AXI DMA is set up to run much before the actual data arrives.