This Figure illustrates example timing on read (MM2S) path in synchronous mode.
Dataflow:
1. After receiving commands on the AXI4-Stream command interface ( s_axis_mm2s_cmd_tvalid ) and if mm2s_allow_addr_req is High, AXI DataMover initiates a read cycle on the AXI4 interface by asserting m_axi_mm2s_arvalid and other address bus signals.
2. It also asserts mm2s_addr_req_posted indicating address is posted on the MMap interface.
3. Read data is stored in internal FIFO if enabled.
4. AXI DataMover starts sending out data on the streaming interface by asserting m_axis_mm2s_tvalid and other associated signals.
5. AXI DataMover asserts mm2s_rd_xfer_cmplt indicating data is completely read on the MMap interface.
6. AXI4-Stream Status interface signals m_axis_mm2s_sts_tvalid and other associated signals are asserted indicating the status for a particular command that was posted on command interface
IMPORTANT: A single parent command can generate multiple child commands on the AXI4 Interface. Status signals are asserted when all child commands are processed.