This Figure illustrates example timing on write (S2MM) path in synchronous mode.
Dataflow:
1. After receiving commands on the AXI4-Stream command interface ( s_axis_s2mm_cmd_tvalid ) and if s2mm_allow_addr_req is High, AXI DataMover initiates write cycles on the AXI4 interface by asserting m_axi_s2mm_awvalid and other address bus signals.
2. AXI DataMover also asserts mm2s_addr_req_posted indicating address is posted on MMap interface.
3. AXI DataMover accepts data on the streaming interface by asserting s_axis_s2mm_tready .
4. Incoming data is stored in FIFO if enabled.
5. AXI DataMover starts sending out data on MMap interface by asserting m_axi_s2mm_wvalid and other associated signals.
6. AXI DataMover asserts s2mm_wr_xfer_cmplt indicating data is completely written on the MMap interface.
7. AXI4-Stream Status interface signals m_axis_s2mm_sts_tvalid and other associated signals are asserted indicating the status for a particular command that was posted on command interface.
8. AXI DataMover also asserts additional signals s2mm_ld_nxt_len along with s2mm_wr_len indicating the burst length of the write transfer to be posted on the AXI4 interface.
IMPORTANT: A single parent command can generate multiple child commands on the AXI4 Interface. Status signals are asserted when all child commands are processed.
Note:
In the absence of any S2MM command, AXI DataMover will pull the
s_axis_s2mm_tready
signal to Low after taking in four beats of streaming data. This will throttle the input data stream. To have a minimum amount of throttling, ensure that a valid command is issued to the S2MM interface much before the actual data arrives.
AXI DataMover does not support null bytes. (
TKEEP
completely deasserted). A start of a streaming packet is identified by
TVALID
while its end is determined by
TLAST
. AXI DataMover does not support sparse/null
TKEEP
between the packet boundaries.
TKEEP
can be sparse only at
TLAST
beat.
TKEEP
can also be sparse at the start of a packet when DRE (unaligned transfers) is enabled.