Example Design - 5.1 English

AXI DataMover LogiCORE IP Product Guide (PG022)

Document ID
PG022
Release Date
2022-04-26
Version
5.1 English

This chapter contains information about the example design provided in the Vivado® Design Suite.

The top module instantiates all components of the core and example design that are needed to implement the design in hardware, as shown in This Figure . This includes clock generator, register configuration, data generator, and data checker modules.

Figure 5-1: Block Diagram of Example Design

X-Ref Target - Figure 5-1

pg022_x13594.jpg

This example design demonstrates transactions on the AXI4 and AXI4-Stream interfaces of the Device Under Test (DUT).

Clock generator : The Clocking Wizard is used to generate the clocks for the example design. When DUT is in synchronous mode, The Clocking Wizard generates a 100 MHz clock for all the AXI interfaces in the example design. When DUT is in asynchronous mode, a 50 MHz clock for the command interface and a 100 MHz clock for the AXI4 and AXI4-Stream interface are generated by the Clocking Wizard. DUT and other modules of the example design are kept under reset until MMCME2 is locked.

Read Data generator : This uses an AXI block RAM which is filled (with a fixed amount of transfers) after MMCM is locked. MM2S channel reads this AXI block RAM and transfers data to the AXI4-Stream interface.

MM2S Command Generator : This module generates one MM2S command.

MM2S STS Checker : This module checks the status that is received from the MM2S channel.

Read Data checker : This module checks the data transferred on the MM2S AXI4-Stream interface.

Write path generator : When the Write (S2MM) channel is configured, this module drives the transactions (with a fixed amount of transfers) on the S2MM AXI4-Stream interface.

S2MM Command Generator : This module generates one S2MM command.

S2MM STS Checker : This module checks the status that is received from the S2MM channel.

Write path checker : This module checks the data received on the AXI4 interface. Data received on the AXI4 interface is also written into another AXI block RAM.

The test starts soon after the MMCM is locked. The 'Done' pin is asserted after the test is completed. If the data transfer is successful then the 'Status' pin is asserted. These two pins can be connected to an LED to know the status of the test.