Features - 5.1 English

AXI DataMover LogiCORE IP Product Guide (PG022)

Document ID
PG022
Release Date
2022-04-26
Version
5.1 English

AXI4 Compliant

Primary AXI4 data width support of 32, 64, 128, 256, 512, and 1,024 bits

Primary AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512 and 1,024 bits

Parameterized Memory Map Burst Lengths of 2, 4, 8, 16, 32, 64, 128, and 256 data beats

Optional Unaligned Address access;
Up to 64 bit address support.

Optional General Purpose Store-And-Forward in both Memory Map to Stream (MM2S) and Stream to Memory Map (S2MM)

Optional Indeterminate Bytes to Transfer (BTT) mode in S2MM

Supports synchronous/asynchronous clocking for Command/Status interface

LogiCORE IP Facts Table

Core Specifics

Supported Device Family (1)

UltraScale+™

UltraScale™

Zynq®-7000 SoC

7 Series FPGAs

Supported User Interfaces

AXI4, AXI4-Stream

Resources

See Table: 7 Series and Zynq-7000 Device Resource Estimates and Table: UltraScale Device Resource Estimates .

Provided with Core

Design Files

VHDL

Example Design

VHDL

Test Bench

VHDL

Constraints File

Delivered during IP generation

Simulation Model

Not Provided

Supported
S/W Driver

N/A

Tested Design Flows (2)

Design Entry

Vivado® Design Suite

Simulation

For supported simulators, see the

Xilinx Design Tools: Release Notes Guide

Synthesis

Not Provided

Support

Release Notes and Known Issues

Master Answer Record: 47651

All Vivado IP

Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:

1. For a complete list of supported devices, see the Vivado IP catalog.

2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide .