Port Descriptions - 5.1 English

AXI DataMover LogiCORE IP Product Guide (PG022)

Document ID
PG022
Release Date
2022-04-26
Version
5.1 English

The AXI DataMover I/O signals are described in Table: I/O Signal Description .

Table 2-6: I/O Signal Description

Signal Name

Interface

Signal
Type

Init Status

Description

Memory Map to Stream Clock and Reset

m_axi_mm2s_aclk

MM2S

Input

Master Clock for MM2S path

m_axi_mm2s_aresetn

MM2S

Input

Master Reset for the MM2S logic. Active-Low assertion sensitivity.

Must be asserted for three clock periods of the slower of m_axi_mm2s_aclk and m_axis_mm2s_cmdsts_aclk.

Memory Map to Stream Soft Shutdown Control

mm2s_halt

MM2S

Input

Active-High input signal requesting that the MM2S function perform a soft shutdown and stop. See MM2S Soft Shutdown .

mm2s_halt_cmplt

MM2S

Output

0

Active-High output signal indicating that the MM2S function has completed a soft shutdown and is stopped. See MM2S Soft Shutdown .

Memory Map to Stream Error Detect

mm2s_err

MM2S

Output

0

MM2S Error Output. This active-High output discrete signal is asserted whenever an Error condition is encountered within the MM2S such as an invalid BTT value of 0. This bit is a “sticky” error indication; after being set it requires an assertion of the m_axi_mm2s_aresetn signal to clear it.

Memory Map to Stream Debug Support

mm2s_dbg_sel(3:0)

MM2S

Input

Reserved for internal Xilinx use. These should be tied to 0.

mm2s_dbg_data(31:0)

MM2S

Output

BEEF0000 (if Omit MM2s)

BEEF1111
(if Full MM2s)

BEEF2222
(if Basic MM2s)

Reserved for internal Xilinx use.

Memory Map to Stream Address Posting Control and Status

mm2s_allow_addr_req

MM2S

Input

Used to control the MM2S in posting an address on the AXI4 Read address channel. A 1 allows posting and a 0 inhibits posting. See Address Posting Control and Status Interface .

mm2s_addr_req_posted

MM2S

Output

0

This output signal is asserted to 1 for one m_axi_mm2s_aclk period for each new address posted to the AXI4 Read Address Channel. See Address Posting Control and Status Interface .

mm2s_rd_xfer_cmplt

MM2S

Output

0

This output signal is asserted to 1 for one m_axi_s2mm_aclk period for each completed AXI4 read transfer (qualified RLAST data beat) clearing the internal read data controller block.

AXI4 Read Interface Signals

m_axi*

M_AXI_MM2S

See the Vivado AXI Reference Guide (UG1037) [Ref 2] for the description of AXI4 Signals.

AXI4-Stream Master Interface Signals

m_axis*

M_AXIS*

See the Vivado AXI Reference Guide (UG1037) [Ref 2] for the description of AXI4 Signals.

Memory Map to Stream Command/Status Channel Asynchronous Clock and Reset

m_axis_mm2s_cmdsts_aclk

MM2S Command & Status

Input

MM2S Command Interface Clock.

This clock is only used if asynchronous clocks are enabled in the Vivado® Integrated Design Environment (IDE). The frequency of this clock is expected to be equal or less than the m_axi_mm2s_aclk.

m_axis_mm2s_
cmdsts_aresetn

MM2S Command & Status

Input

MM2S Command and Status Interface Reset (Active-Low).

This reset input is only used if asynchronous clocks are enabled in the Vivado Integrated Design Environment (IDE).

Must be asserted for three clock periods of the slower of m_axis_mm2s_cmdsts_aclk and m_axi_mm2s_aclk.

AXI4 Slave Stream Interface Signals

s_axis*

S_AXIS*

Input/
Output

Input/
Output

See the Vivado AXI Reference Guide (UG1037) [Ref 2] for the description of AXI4 Signals.

Stream to Memory Map Clock and Reset

m_axi_s2mm_aclk

S2MM

Input

Master Clock for S2MM path

m_axi_s2mm_aresetn

S2MM

Input

Master Reset for the S2MM logic (Active-Low sensitivity).

Must be asserted for three clock periods of the slower of m_axi_s2mm_aclk and m_axis_s2mm_cmdsts_awclk.

Stream to Memory Map Soft Shutdown Control

s2mm_halt

S2MM

Input

Active-High input signal requesting that the S2MM function perform a soft shutdown and stop. See S2MM Soft Shutdown .

s2mm_halt_cmplt

S2MM

Output

0

Active-High output signal indicating that the S2MM function has completed a soft shutdown and is stopped. See S2MM Soft Shutdown .

Stream to Memory Map Error Detect

s2mm_err

S2MM

Output

0

S2MM Error Output. This active-High output discrete signal is asserted whenever an Error condition is encountered within the S2MM such as an invalid BTT of 0 or a Stream overrun or underrun when the S2MM Indeterminate BTT is not enabled. This bit is a “sticky” error indication; after being set it requires an assertion of the m_axi_s2mm_aresetn signal to clear it.

Stream to Memory Map Debug Support

s2mm_dbg_sel(3:0)

S2MM

Input

Reserved for internal Xilinx use.

s2mm_dbg_data(31:0)

S2MM

Output

CAFE0000 (if Omit S2MM)

CAFE1111 (if Full S2MM)

CAFE2222 (if Basic S2MM)

Reserved for internal Xilinx use.

Stream to Memory Map Address Posting Control and Status

s2mm_allow_addr_req

S2MM

Input

Used to control the S2MM in posting an address on the AXI4 Write Address Channel. A 1 allows posting and a 0 inhibits posting. See Address Posting Control and Status Interface .

s2mm_addr_req_posted

S2MM

Output

0

This output signal is asserted to 1 for one m_axi_s2mm_aclk period for each new address posted to the AXI4 Write Address Channel.

s2mm_wr_xfer_cmplt

S2MM

Output

0

This output signal is asserted to 1 for one m_axi_s2mm_aclk period for each completed AXI4 write transfer (qualified WLAST data beat) clearing the internal write data controller block.

s2mm_ld_nxt_len

S2MM

Output

0

This output signal is asserted to 1 for one m_axi_s2mm_aclk period for each AXI4 Write Transfer request to be posted to the AXI4 Write Address channel. This reflects internal queue loading so its assertion is prior to it appearing on the Write Address Channel. This signal qualifies the value on the s2mm_wr_len output port for use by external logic.

s2mm_wr_len

S2MM

Output

0

This bus reflects the value that is placed on the m_axi_s2mm_awlen output (AXI4 Write Address Channel) when it is pulled from the internal queue. The value is only valid when the signal s2mm_ld_nxt_len is asserted.

AXI4 Write Interface Signals

m_axi_s2mm*

M_AXI_S2MM*

See the Vivado AXI Reference Guide (UG1037) [Ref 2] for the description of AXI4 Signals.

Stream to Memory Map Command/Status Channel Asynchronous Clock and Reset

m_axis_s2mm_cmdsts_
awclk

S2MM Command & Status

Input

S2MM Command Interface Clock.

Asynchronous clocks are enabled in the Vivado IDE. The frequency of this clock is expected to be equal or less than the m_axi_s2mm_aclk.

m_axis_s2mm_cmdsts_
aresetn

S2MM Command & Status

Input

S2MM Command Interface Reset (Active-Low).

This reset input is only used if asynchronous clocks are enabled in the Vivado IDE.

Must be asserted for three clock periods of the slower of m_axis_s2mm_cmdsts_awclk and m_axi_s2mm_aclk.