Revision History - 5.1 English

AXI DataMover LogiCORE IP Product Guide (PG022)

Document ID
PG022
Release Date
2022-04-26
Version
5.1 English

The following table shows the revision history for this document.

Date

Version

Revision

04/26/2022

5.1

Updated description for Indeterminate BTT Mode .

Updated the Command Interface section.

04/05/2017

5.1

Updated the description of mm2s_dbg_sel(3:0) in Table 2-6.

Added text to the first paragraph of the Address Posting Control and Status Interface section in Chapter 2. The text describes unconnected and connected signals.

11/18/2015

5.1

Added support for UltraScale+ families.

04/01/2015

5.1

Added support for 64-bit addressing.

11/19/2014

5.1

Revised the description of TKEEP on page 33.

10/01/2014

5.1

Remove non-incrementing Burst transfers from unsupported features.

Minor changes to descriptions in Table 2-5.

Added GUI Parameter to User Parameter Relationship table

04/02/2014

5.1

Updated the Clock Frequencies section.

Many other minor updates.

12/18/2013

5.1

Added UltraScale™ architecture support.

10/02/2013

5.1

Modified demonstration test bench path in Output Generation.

Added example design.

Updated screen displays.

Updated performance numbers in Table 2-1.

Updated Figure 8-2.

Added IP integrator information to Chapter 4.

03/20/2013

5.0

Revision number advanced to 5.0 to align with core version number.

Updated for Vivado design tools and core version 5.0.

Removed all ISE, Virtex®-6, and Spartan®-6 material.

Removed Design Parameters section in Chapter 3.

Added Type field and Maximum Burst Size option.

Updated screen captures in Chapter 4.

Updated many of the I/O signals.

12/18/2012

2.1

Updated for Vivado 2012.4 and ISE v14.4 design tools.

Updated Debugging appendix. Updated core version.

Replaced Figure 1-1 with two new figures.

Updated max frequency numbers and devices.

Removed many rows from resource utilization tables.

Removed Allowable Parameter Combinations section.

Updated screen captures.

Updated output hierarchies.

10/16/2012

2.0.1

Updated for Vivado 2012.3 and ISE v14.3.

Added MM2S and S2MM block Information

Added two figures showing typical use cases for DataMover

Removed AXI Read Master, AXI Write Master sections, AXI DataMover Operation, and Parameter -- I/O Signal Dependencies sections

Added two new sections to Chapter 3:
Example DataMover Read(MM2S) Timing
Example DataMover Write(S2MM) Timing

07/25/2012

2.0

Updated for Vivado 2012.2, Zynq® features, and ISE v14.2

Added Vivado content in Customizing and Generating the Core

07/11/2012

1.1

Template update.

10/19/2011

1.0

Initial Xilinx release.