The AXI DataMover core optionally supports the Data Realignment Engine (DRE). When DRE is enabled, data is realigned to the byte (8 bits) level on the Memory Map datapath. DRE support is provided on the AXI4-Stream interface for TDATA widths up to 64 bits.
If the DRE is enabled, data reads can start from any Buffer Address byte offset, and the read data is aligned such that the first byte read is the first valid byte out on the AXI4-Stream. Similarly, when the DRE is enabled, the writes can happen at any byte offset address. What is considered aligned or unaligned is based on the Memory Map data width. For example, if Memory Map Data Width = 32, data is aligned if it is located at address offsets of 0x0, 0x4, 0x8, 0xC, etc. Data is unaligned if it is located at address offsets of 0x1, 0x2, 0x3 and so forth.
Note: Performing unaligned transfers when DRE is disabled will give unpredictable results.