Vivado Design Suite Debug Feature - 5.1 English

AXI DataMover LogiCORE IP Product Guide (PG022)

Document ID
PG022
Release Date
2022-04-26
Version
5.1 English

There are many tools available to address AXI DataMover core design issues. It is important to know which tools are useful for debugging various situations.

The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into your design. The debug feature also allows you to set trigger conditions to capture application and integrated block port signals in hardware. Captured signals can then be analyzed. This feature in the Vivado Integrated Design Environment (IDE) is used for logic debugging and validation of a design running in Xilinx devices.

The Vivado logic analyzer is used with the logic debug IP cores, including:

ILA 2.0 (and later versions)

VIO 2.0 (and later versions)

See the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 7] .