CDMASR (CDMA Status – Offset 04h) - 4.1 English

31 to 24

IRQDelaySts

00h

RO

SG

Interrupt Delay Time Status. This field reflects the current interrupt delay timer value in the SG Engine.

23 to 16

IRQThresholdSts

01h

RO

SG

Interrupt Threshold Status. This field reflects the current interrupt threshold value in the SG Engine.

15

Reserved

0

RO

N/A

Always read as zero.

14

Err_Irq

0

R/WC

Simple and SG

Interrupt on Error. When set to 1, this bit indicates an interrupt event has been generated due to an error condition. If the corresponding enable bit is set (CDMACR.Err_IrqEn = 1), an interrupt out is generated from the AXI CDMA.

0 = No error Interrupt

1 = Error interrupt active
Writing a 1 to this bit will clear it.

13

Dly_Irq

0

R/WC

SG

Interrupt on Delay. When set to 1, this bit indicates an interrupt event has been generated on a delay timer timeout. If the corresponding enable bit is set (CDMACR.Dly_IrqEn = 1), an interrupt out is generated from the AXI CDMA.

0 = No Delay Interrupt

1 = Delay Interrupt active

Writing a 1 to this bit will clear it.

This bit is cleared whenever CDMACR.SGMode is set to 0.

12

IOC_Irq

0

R/WC

Simple and SG

Interrupt on Complete. When set to 1, this bit indicates an interrupt event has been generated on completion of a DMA transfer (either a Simple or SG). If the corresponding enable bit is set (CDMACR.IOC_IrqEn = 1), an interrupt out is generated from the AXI CDMA.

0 = No IOC Interrupt

1 = IOC Interrupt active

When operating in SG mode, the criteria specified by the interrupt threshold must also be met. Writing a 1 to this bit will clear it.

11

Reserved

0

RO

N/A

Writing to this bit has no effect and it is always read as zeros.

10

SGDecErr

0

RO

SG

Scatter Gather Decode Error. This bit indicates that an AXI decode error has been received by the SG Engine during an AXI transfer (transfer descriptor read or write). This error occurs if the SG Engine issues an address request to an invalid location. This error condition causes the AXI CDMA to gracefully halt. The CDMASR.IDLE bit is set to 1 when the CDMA has completed shut down. The CURDESC_PNTR register is updated with the descriptor pointer value when this error is detected.

0 = No SG Decode Errors

1 = SG Decode Error detected. CDMA Engine halts.

A reset (soft or hard) must be issued to clear the error condition.

9

SGSlvErr

0

RO

SG

Scatter Gather Slave Error. This bit indicates that an AXI slave error response has been received by the SG Engine during an AXI transfer (transfer descriptor read or write). This error condition causes the AXI CDMA to halt gracefully. The CDMASR.IDLE bit is set to 1 when the CDMA has completed shut down. The CURDESC_PNTR register is updated with the descriptor pointer value when this error is detected.

0 = No SG Slave Errors

1 = SG Slave Error detected. CDMA Engine halts.

A reset (soft or hard) must be issued to clear the error condition.

8

SGIntErr

0

RO

SG

Scatter Gather Internal Error. This bit indicates that an internal error has been encountered by the SG Engine. This error condition causes the AXI CDMA to halt gracefully. The CDMASR.IDLE bit is set to 1 when the CDMA has completed shutdown. The CURDESC_PNTR register is updated with the descriptor pointer value when this error is detected.

0 = No SG Internal Errors

1 = SG Internal Error detected. CDMA Engine halts.

A reset (soft or hard) must be issued to clear the error condition.

7

Reserved

0

RO

N/A

Writing to this bit has no effect and it is always read as zeros.

6

DMADecErr

0

RO

Simple and SG

DMA Decode Error. This bit indicates that an AXI decode error has been received by the AXI DataMover. This error occurs if the DataMover issues an address request to an invalid location. This error condition causes the AXI CDMA to halt gracefully. The CDMASR.IDLE bit is set to 1 when the CDMA has completed shut down. The CURDESC_PNTR register is updated with the descriptor pointer value when this error is detected.

0 = No CDMA Decode Errors.

1 = CDMA Decode Error detected. CDMA Engine halts.

A reset (soft or hard) must be issued to clear the error condition.

5

DMASlvErr

0

RO

Simple and SG

DMA Slave Error. This bit indicates that an AXI slave error response has been received by the AXI DataMover during an AXI transfer (read or write). This error condition causes the AXI CDMA to halt gracefully. The CDMASR.IDLE bit is set to 1 when the CDMA has completed shut down. The CURDESC_PNTR register is updated with the descriptor pointer value when this error is detected.

0 = No CDMA Slave Errors.

1 = CDMA Slave Error detected. CDMA Engine halts.

A reset (soft or hard) must be issued to clear the error condition.

4

DMAIntErr

0

RO

Simple and SG

DMA Internal Error. This bit indicates that a internal error has been encountered by the DataMover on the data transport channel. This error can occur if a 0 value BTT (bytes to transfer) is fed to the AXI DataMover or DataMover has an internal processing error. A BTT of 0 only happens if the BTT register is written with zeros (in Simple DMA mode) or a BTT specified in the Control word of a fetched descriptor is set to 0 (SG Mode). This error condition causes the AXI CDMA to halt gracefully. The CDMASR.IDLE bit is set to 1 when the CDMA has completed shut down. CURDESC_PNTR register is updated with the descriptor pointer value when this error is detected.

0 = No CDMA Internal Errors.

1 = CDMA Internal Error detected. CDMA Engine halts.

A reset (soft or hard) must be issued to clear the error condition.

3

SGIncld

See Description

RO

Simple and SG

SG Included. This bit indicates if the AXI CDMA has been implemented with Scatter Gather support included. This is used by application software (drivers) to determine if SG Mode can be utilized.

0 = Scatter Gather not included. Only Simple DMA operations are supported.

1 = Scatter Gather is included. Both Simple DMA and Scatter Gather operations are supported.

2

Reserved

0

RO

N/A

Writing to these bits has no effect and they are always read as zeros.

1

Idle

0

RO

Simple and SG

CDMA Idle. Indicates the state of AXI CDMA operations.

When set and in Simple DMA mode, the bit indicates the programmed transfer has completed and the CDMA is waiting for a new transfer to be programmed. Writing to the bytes to transfer (BTT) register in Simple DMA mode causes the CDMA to start (not Idle).

When set and in SG mode, the bit indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts CDMA SG operations.

0 = Not Idle – Simple or SG DMA operations are in progress.

1 = Idle – Simple or SG operations completed or not started.

0

Reserved

0

RO

SG

Writing to these bits has no effect and they are always read as zeros.

Notes:

1.RO = Read Only. Writing has no effect.

2.R/W = Read/Write