DA (CDMA Destination Address – Offset 20h) - 4.1 English

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)

Document ID
PG034
Release Date
2022-05-18
Version
4.1 English

This register provides the Destination Address for Simple DMA transfers by AXI CDMA.

 

Figure 2-10:      DA Register

X-Ref Target - Figure 2-10

pg034_da_detail_x13285.jpg
Table 2-12:      DA Register Details

Bits

Field Name

Default Value

Access Type

CDMA Mode Used

Description

31to 0

DA

0

RO

Simple

Destination Address Register. This register is used by Simple DMA operations as the starting write address for DMA data transfers. The address value written has restrictions relative to the Source Address and Data Realignment Engine (DRE) inclusion as follows.

If DRE is not included in the AXI CDMA, then the address offset of the Destination address must match that of the Source Address register value. Offset is defined as that portion of a system address that is used to designate a byte position within a single data beat width. For example, a 32-bit data bus has four addressable byte positions within a single data beat (0, 1, 2, and 3). The portion of the address that designates these positions is the offset. The number of address bits used for the offset varies with the transfer bus data width.

The software application should only write to this register when the AXI CDMA is idle (CDMASR.IDLE = 1).

Notes:

1.RO = Read Only. Writing has no effect.

2.R/W = Read/Write